GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
Visible to Intel only — GUID: jng1682631580791
Ixiasoft
Visible to Intel only — GUID: jng1682631580791
Ixiasoft
3.8.1. Enabling the i_tx_cadence_slow_clk_locked Port
If the i_tx_cadence_slow_clk signal does not come directly from TX PLL (word clock or user clock), but rather comes from the other clock source (as might be applicable in FEC Direct modes when using slower clock to accommodate FEC overhead), you must enable the tx_cadence_slow_clk_locked port in the IP parameter editor. The PLL locked output of the other clock source used for slow clock must drive i_tx_cadence_slow_clk_locked.