GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

3.10.1. GTS PMA and FEC Direct PHY Soft CSR Register Map

The GTS PMA and FEC Direct PHY Soft CSR Register Map allows you to read out the status of the GTS PMA/FEC Direct PHY Intel FPGA IP configuration settings, Avalon® memory-mapped ready signals, PMA ready signals, TX PLL locked and RX CDR lock-to-data status signals. It also allows you to control settings for the PMA hard and soft reset signals.

In order to access the soft CSR registers, you must enable following options in the Avalon® Memory-Mapped Interface tab of the GTS PMA/FEC Direct PHY Intel FPGA IP parameter editor:
  • Enable Avalon® Memory Mapped interface
  • Enable Direct PHY soft CSR
Figure 61.  Avalon® Memory-Mapped Interface Parameter Settings For Soft CSR Register Map
Note: You can select the Enable Debug Endpoint on Avalon Interface parameter, if you plan to use the GTS PMA/FEC Direct PHY Intel® FPGA IP debug interconnect fabric to connect the Direct PHY soft CSR registers with the JTAG interface. Refer to Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP for more information about accessing this Avalon® interface.
The starting address for the GTS PMA/FEC Direct PHY Intel FPGA IP soft CSR register through the Avalon® memory-mapped interface is 0x800h. You can refer to the PMA and FEC Direct PHY Soft CSR Register tab in the GTS PMA/FEC Direct PHY Intel FPGA IP Register Map for more details.
Note: The GTS PMA/FEC Direct PHY Intel FPGA IP only has one Avalon® memory-mapped interface that can access the entire address space.