External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

9.3.3. LPDDR5 Interface Design Guidelines

This section describes PCB layout guidelines for LPDDR5 interfaces. Agilex™ 5 E-Series devices Group B support LPDDR5 interfaces for memory down configuration only. Both thin and thick PCB stackups are supported. The maximum supported data rates depend on the selected topology.