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Ixiasoft
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Ixiasoft
3.2. Agilex™ 5 EMIF Architecture: Introduction
The following are key hardware features of the Agilex™ 5 EMIF architecture:
Hard Sequencer
The sequencer employs a hardened processor, and can perform memory calibration for a wide range of protocols. For Agilex™ 5 devices, the sequencer and calibration are localized to each I/O bank.
Hard PHY
The PHY circuitry in Agilex™ 5 devices is hardened in the silicon, which simplifies the challenges of achieving timing closure and minimizing power consumption.
Hard Memory Controller
The hard memory controller reduces latency and minimizes core logic consumption in the external memory interface. The hard memory controller supports the DDR4 and LPDDR4 memory protocols.
High-Speed PHY Clock Tree
Dedicated high speed PHY clock networks clock the I/O buffers in Agilex™ 5 EMIF IP. The PHY clock trees exhibit low jitter and low duty cycle distortion, maximizing the data valid window.
Automatic Clock Phase Alignment
Automatic clock phase alignment circuitry dynamically adjusts the clock phase of core clock networks to match the clock phase of the PHY clock networks. The clock phase alignment circuitry minimizes clock skew that can complicate timing closure in transfers between the FPGA core and the periphery.
Section Content
Agilex 5 EMIF Architecture: I/O Subsystem
Agilex 5 EMIF Architecture: I/O SSM
Agilex 5 EMIF Architecture: HSIO Bank
Agilex 5 EMIF Architecture: I/O Lane
Agilex 5 EMIF Architecture: Input DQS Clock Tree
Agilex 5 EMIF Architecture: PHY Clock Tree
Agilex 5 EMIF Architecture: PLL Reference Clock Networks
Agilex 5 EMIF Architecture: Clock Phase Alignment
User Clock in Different Core Access Modes