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Ixiasoft
Visible to Intel only — GUID: pct1682555307010
Ixiasoft
2. Agilex™ 5 FPGA EMIF IP – Introduction
You can implement the EMIF IP core functions through the Quartus® Prime software.
The External Memory Interfaces Agilex™ 5 FPGA IP (referred to hereafter as the Agilex™ 5 EMIF IP) provides the following components:
- A physical layer interface (PHY) which builds the data path and manages timing transfers between the FPGA and the memory device.
- A memory controller which implements all the memory commands and protocol-level requirements.
For information on the maximum speeds supported by the external memory interface IP, refer to the External Memory Interface Spec Estimator, available here: https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support/emif.html.