External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology

A single channel with 1 rank and x8 memory devices, this interface covers data bytes (DQ/DQS), dddress signals, command signals (BA, BG, RAS, CAS, WE, ACT, PAR), control signals (CKE, CS, ODT) and clocks (CLK)s.

The following figure illustrates the signal connection topology for the 1 rank x 8 memory down configuration.

Figure 25. Signals Connections for Supported Signals in 1 Rank x 8 Discrete Topology

The following table shows specific routing guidelines for 1 rank x 8 discrete memory topology.

Table 106.  Stripline Routing Guidelines for 1 Rank x8 Discrete Memory Topology