External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Agilex™ 5 FPGA EMIF IP - DDR5 Support 8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 10. Agilex™ 5 FPGA EMIF IP – Timing Closure 11. Agilex™ 5 FPGA EMIF IP – Controller Optimization 12. Agilex™ 5 FPGA EMIF IP – Debugging 13. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Lockstep Configuration 3.2.3.2. Pin Placement 3.2.3.3. HSIO Sub-Bank Usage
3.3. Agilex™ 5 EMIF Sequencer x
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions x
3.3.1.1. Mailbox Supported Commands 3.3.1.2. Mailbox Command Definitions
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. Agilex 5 EMIF IP Interfaces for DDR4 4.2. Agilex 5 EMIF IP Interfaces for DDR5 4.3. Agilex 5 EMIF IP Interfaces for LPDDR4 4.4. Agilex 5 EMIF IP Interfaces for LPDDR5 4.5. Agilex 5 EMIF IP Interfaces for the EMIF Calibration Component
4.1. Agilex 5 EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF IP 4.1.2. core_init_n for EMIF IP 4.1.3. usr_async_clk for EMIF IP 4.1.4. usr_clk for EMIF IP 4.1.5. usr_rst_n for EMIF IP 4.1.6. s0_axi4 for EMIF IP 4.1.7. mem for EMIF IP 4.1.8. oct for EMIF IP
4.2. Agilex 5 EMIF IP Interfaces for DDR5 x
4.2.1. ref_clk for EMIF IP 4.2.2. core_init_n for EMIF IP 4.2.3. usr_async_clk for EMIF IP 4.2.4. usr_clk for EMIF IP 4.2.5. usr_rst_n for EMIF IP 4.2.6. s0_axi4 for EMIF IP 4.2.7. mem for EMIF IP 4.2.8. i3c for EMIF IP 4.2.9. mem_lbd for EMIF IP 4.2.10. mem_lbs for EMIF IP 4.2.11. oct for EMIF IP
4.3. Agilex 5 EMIF IP Interfaces for LPDDR4 x
4.3.1. ref_clk for EMIF IP 4.3.2. core_init_n for EMIF IP 4.3.3. usr_async_clk for EMIF IP 4.3.4. usr_clk for EMIF IP 4.3.5. usr_rst_n for EMIF IP 4.3.6. s0_axi4 for EMIF IP 4.3.7. mem for EMIF IP 4.3.8. oct for EMIF IP
4.4. Agilex 5 EMIF IP Interfaces for LPDDR5 x
4.4.1. ref_clk for EMIF IP 4.4.2. core_init_n for EMIF IP 4.4.3. usr_async_clk for EMIF IP 4.4.4. usr_clk for EMIF IP 4.4.5. usr_rst_n for EMIF IP 4.4.6. s0_axi4 for EMIF IP 4.4.7. mem for EMIF IP 4.4.8. oct for EMIF IP
4.5. Agilex 5 EMIF IP Interfaces for the EMIF Calibration Component x
4.5.1. s0_axi4lite_clk for EMIF IP Calibration Component 4.5.2. s0_axi4lite_rst_n for EMIF IP Calibration Component 4.5.3. s0_axil for EMIF IP Calibration Component
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR4 6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.3. Agilex™ 5 EMIF Pin Swapping Guidelines 6.4. DDR4 Layout Design Guidelines
6.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR4 x
6.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for DDR4 6.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions 6.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.1. Agilex™ 5 FPGA EMIF IP Resources 6.2.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 6.2.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP
6.2.1. Agilex™ 5 FPGA EMIF IP Resources x
6.2.1.1. OCT 6.2.1.2. PLL
6.2.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
6.2.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.2.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.2.1.1. Agilex™ 5 FPGA EMIF IP Interface Pins 6.2.2.1.2. Estimating Pin Requirements 6.2.2.1.3. Maximum Number of Interfaces
6.2.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP x
6.2.3.1. Address and Command Pin Placement for DDR4 6.2.3.2. DDR4 Data Width Mapping 6.2.3.3. General Guidelines 6.2.3.4. x4 DIMM Implementation 6.2.3.5. Specific Pin Connection Requirements 6.2.3.6. Command and Address Signals 6.2.3.7. Clock Signals 6.2.3.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.3.1. DDR4 Byte Lane Swapping 6.3.2. DDR4 Address and Command and CLK Lane 6.3.3. DDR4 Interface x8 Data Lane 6.3.4. DDR4 Interface x4 Data Lane
6.4. DDR4 Layout Design Guidelines x
6.4.1. DDR4 PCB Stackup and Design Considerations 6.4.2. DDR4 General Design Considerations 6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies
6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies x
6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology 6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations 6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations 6.4.3.6. DDR4 Simulation Strategy
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support x
7.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR5 7.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
7.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR5 x
7.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for DDR5 7.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions 7.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
7.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 7.2.2. Agilex™ 5 FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 7.2.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP 7.2.5. Agilex™ 5 EMIF Pin Swapping Guidelines
7.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. DIMM Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Agilex™ 5 FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
7.2.3.1. General Guidelines - DDR5 7.2.3.2. x4 DIMM Implementation 7.2.3.3. Specific Pin Connection Requirements 7.2.3.4. Command and Address Signals 7.2.3.5. Clock Signals 7.2.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.2.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP x
7.2.4.1. Address and Command Pin Placement for DDR5 7.2.4.2. DDR5 Data Width Mapping
7.2.5. Agilex™ 5 EMIF Pin Swapping Guidelines x
7.2.5.1. DDR5 Byte Lane Swapping 7.2.5.2. DDR5 Address and Command and CLK Lane 7.2.5.3. DDR5 Interface x8 Data Lane 7.2.5.4. DDR5 Interface x4 Data Lane 7.2.5.5. Pin Swizzling
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
8.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR4 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR4 Layout Design Guidelines
8.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR4 x
8.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for LPDDR4 8.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR4) Parameter Descriptions 8.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR4 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals 8.2.3.5. Address and Command Pin Placement for LPDDR4 8.2.3.6. LPDDR4 Data Width Mapping 8.2.3.7. Pin Swapping Guidelines
8.3. LPDDR4 Layout Design Guidelines x
8.3.1. LPDDR4 PCB Stackup and Design Considerations 8.3.2. LPDDR4 General Design Considerations 8.3.3. LPDDR4 Interface Design Guidelines
8.3.3. LPDDR4 Interface Design Guidelines x
8.3.3.1. LPDDR4 Discrete Component/Memory Down Topology (up to 32 bits interface) 8.3.3.2. LPDDR4 Simulation Strategy
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
9.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR5 9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 9.3. LPDDR5 Layout Design Guidelines
9.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR5 x
9.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for LPDDR5 9.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions 9.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 9.2.2. Agilex™ 5 FPGA EMIF IP Resources 9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
9.2.1.1. Estimating Pin Requirements 9.2.1.2. LPDDR5 Component Options 9.2.1.3. Maximum Number of Interfaces
9.2.2. Agilex™ 5 FPGA EMIF IP Resources x
9.2.2.1. OCT 9.2.2.2. PLL
9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
9.2.3.1. General Guidelines - LPDDR5 9.2.3.2. Specific Pin Connection Requirements 9.2.3.3. Command and Address Signals 9.2.3.4. Clock Signals
9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP x
9.2.4.1. Address and Command Pin Placement for LPDDR5 9.2.4.2. LPDDR5 Data Width Mapping 9.2.4.3. LPDDR5 Byte Lane Swapping
9.3. LPDDR5 Layout Design Guidelines x
9.3.1. LPDDR5 PCB Stackup and Design Considerations 9.3.2. LPDDR5 General Design Considerations 9.3.3. LPDDR5 Interface Design Guidelines
9.3.3. LPDDR5 Interface Design Guidelines x
9.3.3.1. LPDDR5 Discrete Component/Memory Down Topology (Single Rank or Dual-Rank) 9.3.3.2. Example of an LPDDR5 Layout on an Intel FPGA Platform Board 9.3.3.3. LPDDR5 Simulation Strategy
10. Agilex™ 5 FPGA EMIF IP – Timing Closure x
10.1. Timing Closure 10.2. Optimizing Timing
10.1. Timing Closure x
10.1.1. Timing Analysis
10.1.1. Timing Analysis x
10.1.1.1. PHY or Core
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
11.1. Interface Standard 11.2. Bank Management Efficiency 11.3. Data Transfer 11.4. Improving Controller Efficiency
11.4. Improving Controller Efficiency x
11.4.1. Frequency of Operation 11.4.2. Series of Reads or Writes
12. Agilex™ 5 FPGA EMIF IP – Debugging x
12.1. Interface Configuration Performance Issues 12.2. Functional Issue Evaluation 12.3. Timing Issue Characteristics 12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 12.5. Debugging with the External Memory Interface Debug Toolkit 12.6. Generating Traffic with the Test Engine IP 12.7. Guidelines for Developing HDL for Traffic Generator 12.8. Guidelines for Traffic Generator Status Check 12.9. Hardware Debugging Guidelines 12.10. Create a Simplified Design that Demonstrates the Same Issue 12.11. Measure Power Distribution Network 12.12. Measure Signal Integrity and Setup and Hold Margin 12.13. Vary Voltage 12.14. Operate at a Lower Speed 12.15. Determine Whether the Issue Exists in Previous Versions of Software 12.16. Determine Whether the Issue Exists in the Current Version of Software 12.17. Try A Different PCB 12.18. Try Other Configurations 12.19. Debugging Checklist 12.20. Categorizing Hardware Issues 12.21. Signal Integrity Issues 12.22. Characteristics of Signal Integrity Issues 12.23. Evaluating Signal Integrity Issues 12.24. Skew 12.25. Crosstalk 12.26. Power System 12.27. Clock Signals 12.28. Address and Command Signals 12.29. Read Data Valid Window and Eye Diagram 12.30. Write Data Valid Window and Eye Diagram 12.31. Hardware and Calibration Issues 12.32. Memory Timing Parameter Evaluation 12.33. Verify that the Board Has the Correct Memory Component or DIMM Installed
12.1. Interface Configuration Performance Issues x
12.1.1. Interface Configuration Bottleneck and Efficiency Issues
12.2. Functional Issue Evaluation x
12.2.1. Altera IP Memory Model 12.2.2. Vendor Memory Model 12.2.3. Transcript Window Messages
12.3. Timing Issue Characteristics x
12.3.1. Evaluating FPGA Timing Issues 12.3.2. Evaluating External Memory Interface Timing Issues
12.5. Debugging with the External Memory Interface Debug Toolkit x
12.5.1. Prerequisites for Using the EMIF Debug Toolkit 12.5.2. Configuring a Design to Use the Debug Toolkit 12.5.3. Launching the EMIF Debug Toolkit 12.5.4. Using the EMIF Debug Toolkit
12.5.2. Configuring a Design to Use the Debug Toolkit x
12.5.2.1. Generating a Design Example with the Debug Toolkit
12.5.4. Using the EMIF Debug Toolkit x
12.5.4.1. Running Re-Calibration 12.5.4.2. Running the Test Engine
12.8. Guidelines for Traffic Generator Status Check x
12.8.1. Status Check Using the Signal Tap Logic Analyzer 12.8.2. Exporting the Status Interface to the Top-Level Design
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

7.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions

Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 131.  Group: Configuration Save
Display Name Description
Configuration Filepath

Filepath to Save to (.qprs extension)

(Identifier: MEM_CONFIG_FILE_QPRS)
Table 132.  Group: High-Level Parameters
Display Name Description
Memory Format

Specifies the packaging format of the memory device

(Identifier: MEM_FORMAT)
Enable Data Mask

Specifies whether byte masking is to be enabled by the memory.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_DM_EN)
Density of Each Memory Logical Rank

Specifies the density of each memory logical rank in Gbits. For monolithic components, this is the density of the component. For 3D stacked components, the is the density of each die or logical rank.

(Identifier: DDR5_MEM_DEVICE_DENSITY_GBITS)
RDIMM Serial Presence Detect (SPD) Byte 248

Specifies the value of SPD Byte 248 as an integer in decimal.

(Identifier: DDR5_MEM_DEVICE_SPD248_CK_CONTROL_ENABLE)
RDIMM Serial Presence Detect (SPD) Byte 249

Specifies the value of SPD Byte 249 as an integer in decimal.

(Identifier: DDR5_MEM_DEVICE_SPD249_QCA_CS_ENABLE)
RDIMM Serial Presence Detect (SPD) Byte 250

Specifies the value of SPD Byte 250 as an integer in decimal.

(Identifier: DDR5_MEM_DEVICE_SPD250_QCK_SIGNAL_DRIVER_STRENGTH)
RDIMM Serial Presence Detect (SPD) Byte 252

Specifies the value of SPD Byte 252 as an integer in decimal.

(Identifier: DDR5_MEM_DEVICE_SPD252_QCA_QCS_SIGNAL_DRIVER_STRENGTH)
RDIMM Serial Presence Detect (SPD) Byte 254

Specifies the value of SPD Byte 254 as an integer in decimal.

(Identifier: DDR5_MEM_DEVICE_SPD254_CK_CA_CS_SLEW_RATE)
Table 133.  Group: Memory Interface Parameters / Data Bus
Display Name Description
Device DQ Width

If the device is a DIMM: Specifies the full DQ width of the DIMM.

If the interface is composed of discrete components: Specifies the DQ width of each discrete component.

(Identifier: MEM_DEVICE_DQ_WIDTH)
Memory Component Data Width

Specifies the data width of the memory component in bits.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_COMPONENT_DQ_WIDTH)
Burst Length

Specifies the burst length of the memory interface.

(Identifier: DDR5_MEM_DEVICE_BURST_LENGTH)
Table 134.  Group: Memory Interface Parameters / Device Topology
Display Name Description
Number of Ranks per DIMM

Number of ranks per DIMM

Note: This parameter can be auto-computed.

(Identifier: MEM_RANKS_PER_DIMM)
Number of Channels Per DIMM

Number of channels per DIMM

Note: This parameter can be auto-computed.

(Identifier: MEM_CHANNELS_PER_DIMM)
Memory Chip IDs Width

Specifies the width of chip IDs.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_CHIP_ID_WIDTH)
Device Bank Group Address Width

Specifies the width of the bank group address.

(Identifier: DDR5_MEM_DEVICE_BANK_GROUP_ADDR_WIDTH)
Device Bank Address Width

Specifies the width of the bank address.

(Identifier: DDR5_MEM_DEVICE_BANK_ADDR_WIDTH)
Device Row Address Width

Specifies the width of the row address.

(Identifier: DDR5_MEM_DEVICE_ROW_ADDR_WIDTH)
Device Column Address Width

Specifies the width of the column address.

(Identifier: DDR5_MEM_DEVICE_COL_ADDR_WIDTH)
Number of Differential Memory Clock Pairs

Specifies the width of clock interface according to the number of ranks.

(Identifier: DDR5_MEM_DEVICE_CK_WIDTH)
Table 135.  Group: Memory Timing Parameters / Timing Parameters
Display Name Description
Memory Clock Frequency

Specifies the operating frequency of the memory interface in MHz. If you change the memory frequency, you must select a matching Preset from the dropdown (or create a custom one), to update all the timing parameters.

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FREQ_MHZ)
Memory Speed Bin

Specifies the memory speed bin.

(Identifier: DDR5_MEM_DEVICE_SPEEDBIN)
Memory Read Latency

Specifies the read latency of the memory interface in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_CL_CYC)
Memory Write Latency

Specifies the write latency of the memory interface in cycles.

(Identifier: DDR5_MEM_DEVICE_CWL_CYC)
Memory Fine Granularity Refresh Mode

Specifies the Fine Granularity Refresh (FGR) mode of the memory interface.

(Identifier: DDR5_MEM_DEVICE_FINE_GRANULARITY_REFRESH_MODE)
Table 136.  Group: Memory Timing Parameters / Pre- and Post-Amble Options
Display Name Description
Write Preamble Mode

Specifies the write preamble mode of the memory inteface (0: not supported, 1: 2-cycle preamble, 2: 3-cycle preamble, 3: 4-cycle preamble).

(Identifier: DDR5_MEM_DEVICE_WR_PREAMBLE_MODE)
Read Preamble Mode

Specifies the read preamble mode of the memory inteface (0: 1-cycle preamble, 1: 2-cycle preamble, 2: 2-cycle DDR4-style preamble, 3: 3-cycle preamble, 4: 4-cycle preamble).

(Identifier: DDR5_MEM_DEVICE_RD_PREAMBLE_MODE)
Write Postamble Mode

Specifies the write postamble mode of the memory inteface (0: 0.5-cycle postamble, 1: 1.5-cycle postamble).

(Identifier: DDR5_MEM_DEVICE_WR_POSTAMBLE_MODE)
Read Postamble Mode

Specifies the read postamble mode of the memory inteface (0: 0.5-tCK postamble, 1: 1.5-tCK postamble).

(Identifier: DDR5_MEM_DEVICE_RD_POSTAMBLE_MODE)
Table 137.  Group: Memory Timing Parameters / Advanced Timing Parameters
Display Name Description
tREFI1

Specifies the maximum average refresh interval in normal refresh mode in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TREFI1_NS)
tREFI2

Specifies the maximum average refresh interval in fine granularity refresh mode in nanoseconds.

(Identifier: DDR5_MEM_DEVICE_TREFI2_NS)
tREFISB

Specifies the maximum average refresh interval in fine granularity and same bank refresh mode in nanoseconds.

(Identifier: DDR5_MEM_DEVICE_TREFISB_NS)
tCCD_S

Specifies the CAS_n to CAS_n command delay for different bank group in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCCD_S_CYC)
tCCD_L

Specifies the CAS_n to CAS_n command delay for same bank group in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCCD_L_CYC)
tCCD_L_WR

Specifies the write CAS_n to write CAS_n command delay for same bank group in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCCD_L_WR_CYC)
tCCD_L_WR2

Specifies the write CAS_n to write CAS_n command delay for same bank group and the second write is not RMW, in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCCD_L_WR2_CYC)
tCCD_DLR

Specifies the write CAS_n to write CAS_n command delay in different logical ranks, in cycles. Only applicable to 3D stacked devices device.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCCD_DLR_CYC)
tRRD_S

Specifies the Activate-to-Activate command delay to different bank group for 1KB page size in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRRD_S_CYC)
tRRD_L

Specifies the Activate-to-Activate command delay to same bank group for 1KB page size in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRRD_L_CYC)
tRRD_DLR

Specifies the Activate-to-Activate command delay to different logical ranks in cycles. Only applicable to 3D stacked devices.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRRD_DLR_CYC)
tFAW

Specifies the four activate window for 1KB page size in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TFAW_NS)
tFAW_DLR

Specifies the four activate window for different logical ranks in nanoseconds. Only applicable to 3D stacked devices.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TFAW_DLR_NS)
tRFC1

Specifies the refresh operation delay in normal refresh mode in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRFC1_NS)
tRFC2

Specifies the refresh operation delay in fine granularity refresh mode in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRFC2_NS)
tRFCSB

Specifies the refresh operation delay in fine granularity and same bank refresh mode in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRFCSB_NS)
tRCD

Specifies the Activate-to-internal-Read-or-Write delay in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRCD_NS)
tRP

Specifies the row precharge time in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRP_NS)
tRAS

Specifies the Activate-to-Precharge command period in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRAS_NS)
tRC (tRAS+tRP)

Specifies the Activate-to-Activate or Refresh command period in nanoseconds.

(Identifier: DDR5_MEM_DEVICE_TRC_NS)
tREFSBRD

Specifies the same bank refresh to activate delay in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TREFSBRD_NS)
tWR

Specifies the write recovery time in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TWR_NS)
tZQLAT

Specifies the ZQ calibration latch time in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TZQLAT_CYC)
tZQCAL

Specifies the ZQ calibration time in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TZQCAL_NS)
tMRR

Specifies the Mode Register Read (MRR) command period in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TMRR_CYC)
tMRR_P

Specifies the Mode Register Read (MRR) pattern to mode register read pattern command spacing in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TMRR_P_CYC)
tMRW

Specifies the Mode Register Write (MRW) command period in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TMRW_CYC)
tMRD

Specifies the Mode Register Set (MRS) command delay in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TMRD_CYC)
tDFE

Specifies the Decision Feedback Equalization (DFE) Mode Register Write update delay time in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TDFE_NS)
tDLLK

Specifies the timing of DLLK in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TDLLK_CYC)
tWTR_S

Specifies the delay from start of internal write transaction to internal read command for different bank group in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TWTR_S_NS)
tWTR_L

Specifies the delay from start of internal write transaction to internal read command for same bank group in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TWTR_L_NS)
tRTP

Specifies the internal read command to precharge command delay in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRTP_CYC)
tPPD

Specifies the Precharge-to-Precharge delay in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TPPD_CYC)
tPD

Specifies the minimum power down time in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TPD_CYC)
tACTPDEN

Specifies the timing of Activate command to power down entry command in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TACTPDEN_CYC)
tPRPDEN

Specifies the timing of Precharge All Banks (PREab), Precharge Same Bank (PREsb), or Normal Precharge (PREpb) to power down entry command in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TPRPDEN_CYC)
tREFPDEN

Specifies the timing of Refresh All Banks (REFab) or Refresh Same Bank (REFsb) command to power down entry command in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TREFPDEN_CYC)
tXP

Specifies the exit power down to next valid command in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TXP_CYC)
tCPDED

Specifies the command pass disable delay in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCPDED_CYC)
tCSL

Specifies the Self-Refresh CS_n low pulse width in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCSL_NS)
tCKSRX

Specifies the valid clock requirement before SRX in cyclesC.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCKSRX_CYC)
tCSH_SREXIT

Specifies the self-refresh exit CS_n high pulse width in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCSH_SREXIT_NS)
tDQSCK

Specifies the DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TDQSCK_CYC)
tWPRE_EN

Specifies the write preamble enable window in cycles. The window size depends on the write preamble mode.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TWPRE_EN_CYC)
tDQSS

Specifies the host and system voltage/temperature drift window of first rising DQS_t preamble edge relative to CAS Write Latency (CWL) CK_t-CK_c edge in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TDQSS_CYC)
Level Two Title