External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

4.5.2. s0_axi4lite_rst_n for EMIF IP Calibration Component

Axilite reset interface

Table 71.  Interface: s0_axi4lite_rst_nInterface type: reset
Port Name Direction Description
s0_axi4lite_rst_n input Axilite reset