External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Agilex™ 5 FPGA EMIF IP - DDR5 Support 8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 10. Agilex™ 5 FPGA EMIF IP – Timing Closure 11. Agilex™ 5 FPGA EMIF IP – Controller Optimization 12. Agilex™ 5 FPGA EMIF IP – Debugging 13. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Lockstep Configuration 3.2.3.2. Pin Placement 3.2.3.3. HSIO Sub-Bank Usage
3.3. Agilex™ 5 EMIF Sequencer x
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions x
3.3.1.1. Mailbox Supported Commands 3.3.1.2. Mailbox Command Definitions
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. Agilex 5 EMIF IP Interfaces for DDR4 4.2. Agilex 5 EMIF IP Interfaces for DDR5 4.3. Agilex 5 EMIF IP Interfaces for LPDDR4 4.4. Agilex 5 EMIF IP Interfaces for LPDDR5 4.5. Agilex 5 EMIF IP Interfaces for the EMIF Calibration Component
4.1. Agilex 5 EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF IP 4.1.2. core_init_n for EMIF IP 4.1.3. usr_async_clk for EMIF IP 4.1.4. usr_clk for EMIF IP 4.1.5. usr_rst_n for EMIF IP 4.1.6. s0_axi4 for EMIF IP 4.1.7. mem for EMIF IP 4.1.8. oct for EMIF IP
4.2. Agilex 5 EMIF IP Interfaces for DDR5 x
4.2.1. ref_clk for EMIF IP 4.2.2. core_init_n for EMIF IP 4.2.3. usr_async_clk for EMIF IP 4.2.4. usr_clk for EMIF IP 4.2.5. usr_rst_n for EMIF IP 4.2.6. s0_axi4 for EMIF IP 4.2.7. mem for EMIF IP 4.2.8. i3c for EMIF IP 4.2.9. mem_lbd for EMIF IP 4.2.10. mem_lbs for EMIF IP 4.2.11. oct for EMIF IP
4.3. Agilex 5 EMIF IP Interfaces for LPDDR4 x
4.3.1. ref_clk for EMIF IP 4.3.2. core_init_n for EMIF IP 4.3.3. usr_async_clk for EMIF IP 4.3.4. usr_clk for EMIF IP 4.3.5. usr_rst_n for EMIF IP 4.3.6. s0_axi4 for EMIF IP 4.3.7. mem for EMIF IP 4.3.8. oct for EMIF IP
4.4. Agilex 5 EMIF IP Interfaces for LPDDR5 x
4.4.1. ref_clk for EMIF IP 4.4.2. core_init_n for EMIF IP 4.4.3. usr_async_clk for EMIF IP 4.4.4. usr_clk for EMIF IP 4.4.5. usr_rst_n for EMIF IP 4.4.6. s0_axi4 for EMIF IP 4.4.7. mem for EMIF IP 4.4.8. oct for EMIF IP
4.5. Agilex 5 EMIF IP Interfaces for the EMIF Calibration Component x
4.5.1. s0_axi4lite_clk for EMIF IP Calibration Component 4.5.2. s0_axi4lite_rst_n for EMIF IP Calibration Component 4.5.3. s0_axil for EMIF IP Calibration Component
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR4 6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.3. Agilex™ 5 EMIF Pin Swapping Guidelines 6.4. DDR4 Layout Design Guidelines
6.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR4 x
6.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for DDR4 6.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions 6.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.1. Agilex™ 5 FPGA EMIF IP Resources 6.2.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 6.2.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP
6.2.1. Agilex™ 5 FPGA EMIF IP Resources x
6.2.1.1. OCT 6.2.1.2. PLL
6.2.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
6.2.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.2.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.2.1.1. Agilex™ 5 FPGA EMIF IP Interface Pins 6.2.2.1.2. Estimating Pin Requirements 6.2.2.1.3. Maximum Number of Interfaces
6.2.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP x
6.2.3.1. Address and Command Pin Placement for DDR4 6.2.3.2. DDR4 Data Width Mapping 6.2.3.3. General Guidelines 6.2.3.4. x4 DIMM Implementation 6.2.3.5. Specific Pin Connection Requirements 6.2.3.6. Command and Address Signals 6.2.3.7. Clock Signals 6.2.3.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.3.1. DDR4 Byte Lane Swapping 6.3.2. DDR4 Address and Command and CLK Lane 6.3.3. DDR4 Interface x8 Data Lane 6.3.4. DDR4 Interface x4 Data Lane
6.4. DDR4 Layout Design Guidelines x
6.4.1. DDR4 PCB Stackup and Design Considerations 6.4.2. DDR4 General Design Considerations 6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies
6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies x
6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology 6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations 6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations 6.4.3.6. DDR4 Simulation Strategy
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support x
7.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR5 7.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
7.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR5 x
7.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for DDR5 7.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions 7.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
7.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 7.2.2. Agilex™ 5 FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 7.2.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP 7.2.5. Agilex™ 5 EMIF Pin Swapping Guidelines
7.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. DIMM Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Agilex™ 5 FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
7.2.3.1. General Guidelines - DDR5 7.2.3.2. x4 DIMM Implementation 7.2.3.3. Specific Pin Connection Requirements 7.2.3.4. Command and Address Signals 7.2.3.5. Clock Signals 7.2.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.2.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP x
7.2.4.1. Address and Command Pin Placement for DDR5 7.2.4.2. DDR5 Data Width Mapping
7.2.5. Agilex™ 5 EMIF Pin Swapping Guidelines x
7.2.5.1. DDR5 Byte Lane Swapping 7.2.5.2. DDR5 Address and Command and CLK Lane 7.2.5.3. DDR5 Interface x8 Data Lane 7.2.5.4. DDR5 Interface x4 Data Lane 7.2.5.5. Pin Swizzling
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
8.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR4 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR4 Layout Design Guidelines
8.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR4 x
8.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for LPDDR4 8.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR4) Parameter Descriptions 8.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR4 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals 8.2.3.5. Address and Command Pin Placement for LPDDR4 8.2.3.6. LPDDR4 Data Width Mapping 8.2.3.7. Pin Swapping Guidelines
8.3. LPDDR4 Layout Design Guidelines x
8.3.1. LPDDR4 PCB Stackup and Design Considerations 8.3.2. LPDDR4 General Design Considerations 8.3.3. LPDDR4 Interface Design Guidelines
8.3.3. LPDDR4 Interface Design Guidelines x
8.3.3.1. LPDDR4 Discrete Component/Memory Down Topology (up to 32 bits interface) 8.3.3.2. LPDDR4 Simulation Strategy
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
9.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR5 9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 9.3. LPDDR5 Layout Design Guidelines
9.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR5 x
9.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for LPDDR5 9.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions 9.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 9.2.2. Agilex™ 5 FPGA EMIF IP Resources 9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
9.2.1.1. Estimating Pin Requirements 9.2.1.2. LPDDR5 Component Options 9.2.1.3. Maximum Number of Interfaces
9.2.2. Agilex™ 5 FPGA EMIF IP Resources x
9.2.2.1. OCT 9.2.2.2. PLL
9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
9.2.3.1. General Guidelines - LPDDR5 9.2.3.2. Specific Pin Connection Requirements 9.2.3.3. Command and Address Signals 9.2.3.4. Clock Signals
9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP x
9.2.4.1. Address and Command Pin Placement for LPDDR5 9.2.4.2. LPDDR5 Data Width Mapping 9.2.4.3. LPDDR5 Byte Lane Swapping
9.3. LPDDR5 Layout Design Guidelines x
9.3.1. LPDDR5 PCB Stackup and Design Considerations 9.3.2. LPDDR5 General Design Considerations 9.3.3. LPDDR5 Interface Design Guidelines
9.3.3. LPDDR5 Interface Design Guidelines x
9.3.3.1. LPDDR5 Discrete Component/Memory Down Topology (Single Rank or Dual-Rank) 9.3.3.2. Example of an LPDDR5 Layout on an Intel FPGA Platform Board 9.3.3.3. LPDDR5 Simulation Strategy
10. Agilex™ 5 FPGA EMIF IP – Timing Closure x
10.1. Timing Closure 10.2. Optimizing Timing
10.1. Timing Closure x
10.1.1. Timing Analysis
10.1.1. Timing Analysis x
10.1.1.1. PHY or Core
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
11.1. Interface Standard 11.2. Bank Management Efficiency 11.3. Data Transfer 11.4. Improving Controller Efficiency
11.4. Improving Controller Efficiency x
11.4.1. Frequency of Operation 11.4.2. Series of Reads or Writes
12. Agilex™ 5 FPGA EMIF IP – Debugging x
12.1. Interface Configuration Performance Issues 12.2. Functional Issue Evaluation 12.3. Timing Issue Characteristics 12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 12.5. Debugging with the External Memory Interface Debug Toolkit 12.6. Generating Traffic with the Test Engine IP 12.7. Guidelines for Developing HDL for Traffic Generator 12.8. Guidelines for Traffic Generator Status Check 12.9. Hardware Debugging Guidelines 12.10. Create a Simplified Design that Demonstrates the Same Issue 12.11. Measure Power Distribution Network 12.12. Measure Signal Integrity and Setup and Hold Margin 12.13. Vary Voltage 12.14. Operate at a Lower Speed 12.15. Determine Whether the Issue Exists in Previous Versions of Software 12.16. Determine Whether the Issue Exists in the Current Version of Software 12.17. Try A Different PCB 12.18. Try Other Configurations 12.19. Debugging Checklist 12.20. Categorizing Hardware Issues 12.21. Signal Integrity Issues 12.22. Characteristics of Signal Integrity Issues 12.23. Evaluating Signal Integrity Issues 12.24. Skew 12.25. Crosstalk 12.26. Power System 12.27. Clock Signals 12.28. Address and Command Signals 12.29. Read Data Valid Window and Eye Diagram 12.30. Write Data Valid Window and Eye Diagram 12.31. Hardware and Calibration Issues 12.32. Memory Timing Parameter Evaluation 12.33. Verify that the Board Has the Correct Memory Component or DIMM Installed
12.1. Interface Configuration Performance Issues x
12.1.1. Interface Configuration Bottleneck and Efficiency Issues
12.2. Functional Issue Evaluation x
12.2.1. Altera IP Memory Model 12.2.2. Vendor Memory Model 12.2.3. Transcript Window Messages
12.3. Timing Issue Characteristics x
12.3.1. Evaluating FPGA Timing Issues 12.3.2. Evaluating External Memory Interface Timing Issues
12.5. Debugging with the External Memory Interface Debug Toolkit x
12.5.1. Prerequisites for Using the EMIF Debug Toolkit 12.5.2. Configuring a Design to Use the Debug Toolkit 12.5.3. Launching the EMIF Debug Toolkit 12.5.4. Using the EMIF Debug Toolkit
12.5.2. Configuring a Design to Use the Debug Toolkit x
12.5.2.1. Generating a Design Example with the Debug Toolkit
12.5.4. Using the EMIF Debug Toolkit x
12.5.4.1. Running Re-Calibration 12.5.4.2. Running the Test Engine
12.8. Guidelines for Traffic Generator Status Check x
12.8.1. Status Check Using the Signal Tap Logic Analyzer 12.8.2. Exporting the Status Interface to the Top-Level Design
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

7.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for DDR5

Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 111.  Group: Example Design / Example Design
Display Name Description
HDL Selection

This option lets you choose the format of HDL in which generated simulation and synthesis files are created. You can select either Verilog or VHDL.

(Identifier: EX_DESIGN_HDL_FORMAT)
Synthesis

Generate Synthesis Example Design

(Identifier: EX_DESIGN_GEN_SYNTH)
Simulation

Generate Simulation Example Design

(Identifier: EX_DESIGN_GEN_SIM)
Core Clock Freq

Frequency of the core clock in MHz. This clock drives the traffic generator and NoC initiator (If in NoC mode)

Note: This parameter can be auto-computed.

(Identifier: EX_DESIGN_CORE_CLK_FREQ_MHZ)
Core Refclk Freq

PLL reference clock frequency in MHz for PLL supplying the core clock

(Identifier: EX_DESIGN_CORE_REFCLK_FREQ_MHZ)
Traffic Generator Remote Access

Specifies whether the Traffic Generator control and status registers are accessible via JTAG, exported to the fabric, or just disabled

(Identifier: EX_DESIGN_HYDRA_REMOTE)
Table 112.  Group: General IP Parameters / High-Level Parameters
Display Name Description
Technology Generation

Denotes the specific memory technology generation to be used

Note: This parameter can be auto-computed.

(Identifier: MEM_TECHNOLOGY)
Memory Format

Specifies the packaging format of the memory device

(Identifier: MEM_FORMAT)
Memory Device Topology

Topology used by memory device

(Identifier: MEM_TOPOLOGY)
Memory Ranks

Total number of physical ranks in the interface

(Identifier: MEM_NUM_RANKS)
Number of Channels

Number of channels

(Identifier: MEM_NUM_CHANNELS)
Device DQ Width

If the device is a DIMM: Specifies the full DQ width of the DIMM.

If the interface is composed of discrete components: Specifies the DQ width of each discrete component.

(Identifier: MEM_DEVICE_DQ_WIDTH)
Number of Components Per Rank

Number of components per rank

(Identifier: MEM_COMPS_PER_RANK)
ECC Mode

Specifies the type of ECC (if any) and the required number of side-band bits per channel that will be used by this EMIF instance. While not all required side-band bits necessarily carry ECC bits, all need to be connected to the memory device. If enabling ECC requires more side-band bits than necessary ECC bits, then ECC bits are transmitted on the least significant side-band bits.

Note: This parameter can be auto-computed.

(Identifier: CTRL_ECC_MODE)
Enable Extra DQ Byte Lane

Augment a given memory interface with 8 extra DQ bits. These extra bits are accessed via the WUSER and RUSER ports on the PHY's AXI4 interface. The AXI4 WUSER and RUSER ports are 64-bit wide. In this release, this option can only augment a given 32/64-bit DDR4 in interface configured in fabric-synchronous mode without controller generated ECC bits.

Note: This parameter can be auto-computed.

(Identifier: AXI4_USER_DATA_ENABLE)
Total DQ Width

(Derived Parameter) This will be the width (in bits) of the mem_dq port on the memory interface.

For a component interface, it is calculated based on: (MEM_COMPS_PER_RANK * MEM_DEVICE_DQ_WIDTH + (8 bits if Side-band ECC is enabled, or 8 bits if AXI4 User Data is enabled in fabric modes, or 4 bits if AXI4 User Data is enabled in NoC mode)) * MEM_NUM_CHANNELS

For a DIMM-based interface, it is just MEM_DEVICE_DQ_WIDTH + (8 bits if side-band ECC is enabled, or 8 bits if AXI4 User Data is enabled in fabric modes, or 4 bits if AXI4 User Data is enabled in NoC mode) * MEM_NUM_CHANNELS.

(Identifier: MEM_TOTAL_DQ_WIDTH)
Memory Clock Frequency

Specifies the operating frequency of the memory interface in MHz. If you change the memory frequency, you must select a matching Preset from the dropdown (or create a custom one), to update all the timing parameters.

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FREQ_MHZ)
Instance ID

Instance ID of the EMIF IP. EMIF in the same bank, or connected to related user logic (e.g. to the same INIU), should have unique IDs in order to distinguish them when using the side-band interface. Valid values are 0-6.

(Identifier: INSTANCE_ID)
Table 113.  Group: General IP Parameters / Memory Device Preset Selection
Display Name Description
Use Memory Device Preset from file

Specifies whether MEM_PRESET_ID will be a value from Quartus (if false), or a value from a custom preset file path (if true)

(Identifier: MEM_PRESET_FILE_EN)
Memory Preset custom file path

Path to a .qprs file on the users disk

(Identifier: MEM_PRESET_FILE_QPRS)
Memory Preset

The name of a preset that the user would like to load, describing the memory device that this emif will be targeting.

Note: This parameter can be auto-computed.

(Identifier: MEM_PRESET_ID)
Table 114.  Group: General IP Parameters / Advanced Parameters / PHY / Topology
Display Name Description
Asynchronous Enable

Specifies whether the user logic is clocked based on the clock provided by the IP (Sync), or by a separate user clock (Async). If true - async mode is used, if false - sync mode is used.

(Identifier: PHY_ASYNC_EN)
AC Placement

Indicates location on the device where the interface will reside (specifically, the location of the AC lanes in terms IO BANK and TOP vs BOT part of the IO BANK). Legal ranges are derived from device floorplan. By default (value=AUTO), the most optimal location is selected (to maximize available frequency and data width).

Note: This parameter can be auto-computed.

(Identifier: PHY_AC_PLACEMENT)
PLL Reference Clock Frequency

Specifies what PLL reference clock frequency the user will supply. It is recommended to use the fastest possible PLL reference clock frequency because it leads to better jitter performance.

Note: This parameter can be auto-computed.

(Identifier: PHY_REFCLK_FREQ_MHZ)
Table 115.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings
Display Name Description
Voltage

The voltage level for the I/O pins driving the signals between the memory device and the FPGA memory interface.

(Identifier: PHY_IO_VOLTAGE)
Table 116.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / Address/Command
Display Name Description
Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the Address/Command Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: GRP_PHY_AC_X_R_S_AC_OUTPUT_OHM)
Table 117.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / Memory Clock
Display Name Description
Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the CK Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: GRP_PHY_CLK_X_R_S_CK_OUTPUT_OHM)
Table 118.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / Data Bus
Display Name Description
I/O Standard

Specifies the I/O electrical standard for the data bus pins. The selected I/O standard configures the circuit within the I/O buffer to match the industry standard.

(Identifier: GRP_PHY_DATA_X_DQ_IO_STD_TYPE)
Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: GRP_PHY_DATA_X_R_S_DQ_OUTPUT_OHM)
Slew Rate

Specifies the slew rate of the data bus pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the slew rate that provides the best eye opening for the data bus signals.

(Identifier: GRP_PHY_DATA_X_DQ_SLEW_RATE)
Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: GRP_PHY_DATA_X_R_T_DQ_INPUT_OHM)
Initial Vrefin

Specifies the initial value for the reference voltage on the data pins(Vrefin). The specified value serves as a starting point and may be overridden by calibration to provide better timing margins.

(Identifier: GRP_PHY_DATA_X_DQ_VREF)
Table 119.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / PHY Inputs
Display Name Description
PLL Reference Clock Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design.

(Identifier: GRP_PHY_IN_X_R_T_REFCLK_INPUT_OHM)
Table 120.  Group: General IP Parameters / Advanced Parameters / FPGA I/O / FPGA I/O Settings / Decision Feedback Equilization (DFE)
Display Name Description
DFE Tap 1

This parameter allows you to select the amount of bias used on tap 1 of the FPGA DFE

(Identifier: GRP_PHY_DFE_X_TAP_1)
DFE Tap 2

This parameter allows you to select the amount of bias used on tap 2 of the FPGA DFE

(Identifier: GRP_PHY_DFE_X_TAP_2)
DFE Tap 3

This parameter allows you to select the amount of bias used on tap 3 of the FPGA DFE

(Identifier: GRP_PHY_DFE_X_TAP_3)
DFE Tap 4

This parameter allows you to select the amount of bias used on tap 4 of the FPGA DFE

(Identifier: GRP_PHY_DFE_X_TAP_4)
Table 121.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Data Bus On-Die Termination (ODT)
Display Name Description
Target Write Termination

Specifies the target termination to be used during a write

(Identifier: GRP_MEM_ODT_DQ_X_TGT_WR)
Non-Target Write Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration during a write

(Identifier: GRP_MEM_ODT_DQ_X_NON_TGT_WR)
Non-Target Read Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration during a read

(Identifier: GRP_MEM_ODT_DQ_X_NON_TGT_RD)
Idle Termination

Specifies the termination to be used for RTT_PARK and DQS_RTT_PARK. For power savings it is recommended to leave this as disabled.

(Identifier: GRP_MEM_ODT_DQ_X_IDLE)
Drive Strength

Specifies the termination to be used when driving read data from memory

(Identifier: GRP_MEM_ODT_DQ_X_RON)
Table 122.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Data Bus Reference Voltage (Vref)
Display Name Description
VrefDQ Value

Specifies the initial VrefDQ value to be used

(Identifier: GRP_MEM_DQ_VREF_X_VALUE)
Table 123.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Address/Command Bus On-Die Termination (ODT)
Display Name Description
CA Termination

Specifies the termination to be used for the CA bus. This setting only applies to Group B, Group A will always be unterminated.

(Identifier: GRP_MEM_ODT_CA_X_CA)
CS Termination

Specifies the termination to be used for the CS bus. This setting only applies to Group B, Group A will always be unterminated.

(Identifier: GRP_MEM_ODT_CA_X_CS)
CK Termination

Specifies the termination to be used for the CK bus. This setting only applies to Group B, Group A will always be unterminated.

(Identifier: GRP_MEM_ODT_CA_X_CK)
Table 124.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Address/Command Bus Reference Voltage (Vref)
Display Name Description
VrefCA Value

Specifies the initial VrefCA value to be used

(Identifier: GRP_MEM_VREF_CA_X_CA_VALUE)
VrefCS Value

Specifies the initial VrefCS value to be used

(Identifier: GRP_MEM_VREF_CA_X_CS_VALUE)
Table 125.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / Decision Feedback Equilization (DFE)
Display Name Description
DFE Tap 1

This parameter allows you to select the amount of bias used on tap 1 of the memory DFE

(Identifier: GRP_MEM_DFE_X_TAP_1)
DFE Tap 2

This parameter allows you to select the amount of bias used on tap 2 of the memory DFE

(Identifier: GRP_MEM_DFE_X_TAP_2)
DFE Tap 3

This parameter allows you to select the amount of bias used on tap 3 of the memory DFE

(Identifier: GRP_MEM_DFE_X_TAP_3)
DFE Tap 4

This parameter allows you to select the amount of bias used on tap 4 of the memory DFE

(Identifier: GRP_MEM_DFE_X_TAP_4)
Table 126.  Group: General IP Parameters / Advanced Parameters / Mem I/O / Memory I/O Settings / RCD Control Word Settings
Display Name Description
RCD CA Input Termination

This parameter allows you to select the input bus termination of RCD CA input bus. See JEDEC specifications on DDR4CD02 and DDR5RCD04 for the pins covered.

(Identifier: GRP_MEM_RCD_DCA_IBT)
RCD CS Input Termination

This parameter allows you to select the input bus termination of RCD CS input bus. See JEDEC specifications on DDR4CD02 and DDR5RCD04 for the pins covered.

(Identifier: GRP_MEM_RCD_DCS_IBT)
RCD CK Input Termination

This parameter allows you to select the input bus termination of CK input bus. See JEDEC specifications on DDR5RCD04 for the pins covered.

(Identifier: GRP_MEM_RCD_DCK_IBT)
RCD Error Input Termination

This parameter allows you to select the input bus termination of DERROR input bus. See JEDEC specification on DDR5RCD04 for the pins covered.

(Identifier: GRP_MEM_RCD_DERROR_IBT)
Table 127.  Group: General IP Parameters / Advanced Parameters / AXI Settings / AXI Interface Settings
Display Name Description
Enable Debug Tools

If enabled, the AXI-L port will be connected to SLD nodes, allowing for a system-console avalon manager interface to interact with this AXI-L subordinate interface.

(Identifier: DEBUG_TOOLS_EN)
AXI-Lite Port Access Mode

Specifies whether the AXI-Lite port is connected to the fabric, the NOC, or disabled

Note: This parameter can be auto-computed.

(Identifier: AXI_SIDEBAND_ACCESS_MODE)
Table 128.  Group: General IP Parameters / Advanced Parameters / Additional Parameters / Additional String Parameters
Display Name Description
User Extra Parameters

Semi-colon seperated list of key/value pairs of extra parameters

(Identifier: USER_EXTRA_PARAMETERS)
Table 129.  Group: Example Design / Performance Monitor
Display Name Description
Enable performance monitoring

Enable performance monitor on all channels for measuring read/write transaction metrics

(Identifier: EX_DESIGN_PMON_ENABLED)
Table 130.  Group: Example Design / Traffic Generator Program
Display Name Description
Traffic Generator Program

Specifies the traffic pattern to be run.

(Identifier: EX_DESIGN_HYDRA_PROG)
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