External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

9.3.3.3. LPDDR5 Simulation Strategy

The simulation strategy is divided into two parts:

  • Data Signal signal integrity simulation with respect to their DQS on the worse signal integrity of a data group (considering the longest routing and max vertical crosstalk between signals).
  • CS/CTRL/CMD signal integrity simulation with respect to their CLK signals on the worst signal integrity of those signals (considering the longest routing and max vertical crosstalk between signals).

Altera recommends that a signal integrity engineer review the layout and pick the worst data group (select a victim and surrounded aggressors and DQS in the group) that has the worst signal integrity performance on the layout, e.g the worst crosstalk (coupling between deep vertical vias), long trace routing and maximum reflection on routing path due to long via stubs if backdrilling is not applied.

Designers must perform the signal integrity simulation of the board layout for the selected victim surrounded by aggressor signals.

You must perform the channel analysis in the time domain, using a pseudorandom binary sequence (PRBS) pattern for I/O signal generation, while the channel is built by using actual per-pin package models at both ends, including PCB model in the format of scattering parameter along with I/O buffer model at both ends. An I/O buffer IBIS model is used for DDR4 interface signal integrity simulation. Evaluate the eye diagram after the simulation, to ensure the eye specification is met at both ends.