Visible to Intel only — GUID: roe1682598229443
Ixiasoft
Visible to Intel only — GUID: roe1682598229443
Ixiasoft
12.24. Skew
Trace length variations cause data valid window variations between the signals, reducing margin. For example, DDR4-3200 at 1600 MHz has a data valid window that is smaller than 313 ps. Trace length skew or crosstalk can reduce this data valid window further, making it difficult to design a reliably operating memory interface. Ensure that the skew figure previously entered into the Altera FPGA IP matches that actually achieved on the PCB, otherwise Quartus® Prime timing analysis of the interface is accurate.