External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

9.3.3.2. Example of an LPDDR5 Layout on an Intel FPGA Platform Board

The following figure shows the layout example of a single rank LPDDR5 x 32 bit device with pitch size of 0.7×0.8 mm in an Altera FPGA platform design. It uses a thick PCB (120mil stackup) with micro vias and through vias with backdrill. The LPDDR5 signal routing is on upper layers to avoid vertical crosstalk on interface and achieve high performance.

Figure 70. Board Layout and Via Pattern for Single Rank LPDDR5 x32 Device on an Altera FPGA Platform Design