External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

8.2.3.5. Address and Command Pin Placement for LPDDR4

Agilex™ 5 FPGA IP for LPDDR4 supports fixed address and command pin placements as shown in the following table.

The IP supports up to two ranks.

Address/Command Lane Index Within Byte Lane LPDDR4
AC1 11  
10  
9  
8  
7 MEM_CK_C
6 MEM_CK_T
5  
4  
3 MEM_RESET_N
2 OCT_RZQIN
1  
0  
AC0 11 Differential "N-side" reference clock input site
10 Differential "P-side" reference clock input site
9 MEM_CS[1]
8 MEM_CS[0]
7 MEM_CKE[1]
6 MEM_CKE[0]
5 MEM_CA[5]
4 MEM_CA[4]
3 MEM_CA[3]
2 MEM_CA[2]
1 MEM_CA[1]
0 MEM_CA[0]