External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public

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12.8.2. Exporting the Status Interface to the Top-Level Design

Do not perform this procedure if you plan to observe signal activity through the Signal Tap Logic Analyzer only.

Using the Agilex™ 5 FPGA EMIF IP design example, perform the following steps to export the traffic generator traffic signals:

  1. Navigate to the IP Components tab in the Project Navigator, and click ed_synth.qsys to open the design in the Platform Designer.
    Figure 79. 
  2. Click on Test Engine Intel FPGA IP and go to the Remote Access tab.
  3. Check the Export status interface box.
  4. Note the status port available in the IP instance. Export the status signal to the top-level design.
    Figure 80. 
  5. Save the design.
  6. Click Sync System Infos and Generate HDL.
    Figure 81. 
  7. Compile the design. You can observe the status_status_done and status_status_error signals exported at the top level of the traffic_generator instance.
    Figure 82.