External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

7.2.3.5. Clock Signals

DDR5 SDRAM devices use CK_t and CK_c signals to clock the address and command signals into the memory.
The memory uses these clock signals to generate the DQS signal during a read through the DLL inside the memory.