External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning

The following topics provide guidelines on pin placement for external memory interfaces.

Typically, all external memory interfaces require the following FPGA resources:

  • Interface pins.
  • PLL and clock network.
  • RZQ pins.
  • Other FPGA resources — for example, core fabric logic and debug interfaces.
  • Once all the requirements for your external memory interface are known, you can begin planning your system.