External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

4.1.1. ref_clk for EMIF IP

PLL reference clock input

Table 31.  Interface: ref_clkInterface type: clock
Port Name Direction Description
ref_clk input PLL reference clock input