External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank

Each I/O row contains up to two HSIO banks; the exact number of banks depends on device size and pin package. EMIF interfaces can be implemented on HSIO banks only.

Each HSIO bank consists of two sub-banks, and each sub-bank contains the following components:

  • I/O PLL and PHY clock trees
  • DLL
  • Input DQS clock trees
  • 48 pins, organized into four I/O lanes of 12 pins each
Figure 3. HSIO Bank Architecture in Agilex™ 5 Devices

I/O Bank Architecture

Within an HSIO bank, the top sub-bank is pin indexes P95:P48, and the bottom sub-bank is pin indexes P47:P0.

Agilex™ 5 devices have two hard memory controllers: primary and secondary. The primary hard memory controller has access to all 96 pins in an HSIO bank. The secondary hard memory controller has access only to the top sub-bank. In the above figure, the yellow signals highlight the connections for the secondary hard memory controller, while the red signals show the connections for the primary hard memory controller. The green signals show where both hard memory controllers are bypassed to provide access to the PHY from the core logic.

Package B18A on Agilex™ 5 E-Series devices has only one HSIO bank. Only pins on the top sub-bank are bonded out. Due to the limited HSIO pins available, this package does not support EMIF.