External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

4.2.2. core_init_n for EMIF IP

An input to indicate that core configuration is complete

Table 41.  Interface: core_init_nInterface type: reset
Port Name Direction Description
core_init_n input Core init signal going into EMIF. Used to generate the reset signal on the core-EMIF interface in fabric modes.