External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Agilex™ 5 FPGA EMIF IP - DDR5 Support 8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 10. Agilex™ 5 FPGA EMIF IP – Timing Closure 11. Agilex™ 5 FPGA EMIF IP – Controller Optimization 12. Agilex™ 5 FPGA EMIF IP – Debugging 13. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Lockstep Configuration 3.2.3.2. Pin Placement 3.2.3.3. HSIO Sub-Bank Usage
3.3. Agilex™ 5 EMIF Sequencer x
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions x
3.3.1.1. Mailbox Supported Commands 3.3.1.2. Mailbox Command Definitions
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. Agilex 5 EMIF IP Interfaces for DDR4 4.2. Agilex 5 EMIF IP Interfaces for DDR5 4.3. Agilex 5 EMIF IP Interfaces for LPDDR4 4.4. Agilex 5 EMIF IP Interfaces for LPDDR5 4.5. Agilex 5 EMIF IP Interfaces for the EMIF Calibration Component
4.1. Agilex 5 EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF IP 4.1.2. core_init_n for EMIF IP 4.1.3. usr_async_clk for EMIF IP 4.1.4. usr_clk for EMIF IP 4.1.5. usr_rst_n for EMIF IP 4.1.6. s0_axi4 for EMIF IP 4.1.7. mem for EMIF IP 4.1.8. oct for EMIF IP
4.2. Agilex 5 EMIF IP Interfaces for DDR5 x
4.2.1. ref_clk for EMIF IP 4.2.2. core_init_n for EMIF IP 4.2.3. usr_async_clk for EMIF IP 4.2.4. usr_clk for EMIF IP 4.2.5. usr_rst_n for EMIF IP 4.2.6. s0_axi4 for EMIF IP 4.2.7. mem for EMIF IP 4.2.8. i3c for EMIF IP 4.2.9. mem_lbd for EMIF IP 4.2.10. mem_lbs for EMIF IP 4.2.11. oct for EMIF IP
4.3. Agilex 5 EMIF IP Interfaces for LPDDR4 x
4.3.1. ref_clk for EMIF IP 4.3.2. core_init_n for EMIF IP 4.3.3. usr_async_clk for EMIF IP 4.3.4. usr_clk for EMIF IP 4.3.5. usr_rst_n for EMIF IP 4.3.6. s0_axi4 for EMIF IP 4.3.7. mem for EMIF IP 4.3.8. oct for EMIF IP
4.4. Agilex 5 EMIF IP Interfaces for LPDDR5 x
4.4.1. ref_clk for EMIF IP 4.4.2. core_init_n for EMIF IP 4.4.3. usr_async_clk for EMIF IP 4.4.4. usr_clk for EMIF IP 4.4.5. usr_rst_n for EMIF IP 4.4.6. s0_axi4 for EMIF IP 4.4.7. mem for EMIF IP 4.4.8. oct for EMIF IP
4.5. Agilex 5 EMIF IP Interfaces for the EMIF Calibration Component x
4.5.1. s0_axi4lite_clk for EMIF IP Calibration Component 4.5.2. s0_axi4lite_rst_n for EMIF IP Calibration Component 4.5.3. s0_axil for EMIF IP Calibration Component
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR4 6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.3. Agilex™ 5 EMIF Pin Swapping Guidelines 6.4. DDR4 Layout Design Guidelines
6.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR4 x
6.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for DDR4 6.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions 6.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.1. Agilex™ 5 FPGA EMIF IP Resources 6.2.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 6.2.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP
6.2.1. Agilex™ 5 FPGA EMIF IP Resources x
6.2.1.1. OCT 6.2.1.2. PLL
6.2.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
6.2.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.2.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.2.1.1. Agilex™ 5 FPGA EMIF IP Interface Pins 6.2.2.1.2. Estimating Pin Requirements 6.2.2.1.3. Maximum Number of Interfaces
6.2.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP x
6.2.3.1. Address and Command Pin Placement for DDR4 6.2.3.2. DDR4 Data Width Mapping 6.2.3.3. General Guidelines 6.2.3.4. x4 DIMM Implementation 6.2.3.5. Specific Pin Connection Requirements 6.2.3.6. Command and Address Signals 6.2.3.7. Clock Signals 6.2.3.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.3.1. DDR4 Byte Lane Swapping 6.3.2. DDR4 Address and Command and CLK Lane 6.3.3. DDR4 Interface x8 Data Lane 6.3.4. DDR4 Interface x4 Data Lane
6.4. DDR4 Layout Design Guidelines x
6.4.1. DDR4 PCB Stackup and Design Considerations 6.4.2. DDR4 General Design Considerations 6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies
6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies x
6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology 6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations 6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations 6.4.3.6. DDR4 Simulation Strategy
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support x
7.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR5 7.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
7.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR5 x
7.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for DDR5 7.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions 7.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
7.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 7.2.2. Agilex™ 5 FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 7.2.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP 7.2.5. Agilex™ 5 EMIF Pin Swapping Guidelines
7.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. DIMM Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Agilex™ 5 FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
7.2.3.1. General Guidelines - DDR5 7.2.3.2. x4 DIMM Implementation 7.2.3.3. Specific Pin Connection Requirements 7.2.3.4. Command and Address Signals 7.2.3.5. Clock Signals 7.2.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.2.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP x
7.2.4.1. Address and Command Pin Placement for DDR5 7.2.4.2. DDR5 Data Width Mapping
7.2.5. Agilex™ 5 EMIF Pin Swapping Guidelines x
7.2.5.1. DDR5 Byte Lane Swapping 7.2.5.2. DDR5 Address and Command and CLK Lane 7.2.5.3. DDR5 Interface x8 Data Lane 7.2.5.4. DDR5 Interface x4 Data Lane 7.2.5.5. Pin Swizzling
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
8.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR4 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR4 Layout Design Guidelines
8.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR4 x
8.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for LPDDR4 8.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR4) Parameter Descriptions 8.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR4 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals 8.2.3.5. Address and Command Pin Placement for LPDDR4 8.2.3.6. LPDDR4 Data Width Mapping 8.2.3.7. Pin Swapping Guidelines
8.3. LPDDR4 Layout Design Guidelines x
8.3.1. LPDDR4 PCB Stackup and Design Considerations 8.3.2. LPDDR4 General Design Considerations 8.3.3. LPDDR4 Interface Design Guidelines
8.3.3. LPDDR4 Interface Design Guidelines x
8.3.3.1. LPDDR4 Discrete Component/Memory Down Topology (up to 32 bits interface) 8.3.3.2. LPDDR4 Simulation Strategy
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
9.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR5 9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 9.3. LPDDR5 Layout Design Guidelines
9.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR5 x
9.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for LPDDR5 9.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions 9.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 9.2.2. Agilex™ 5 FPGA EMIF IP Resources 9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
9.2.1.1. Estimating Pin Requirements 9.2.1.2. LPDDR5 Component Options 9.2.1.3. Maximum Number of Interfaces
9.2.2. Agilex™ 5 FPGA EMIF IP Resources x
9.2.2.1. OCT 9.2.2.2. PLL
9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
9.2.3.1. General Guidelines - LPDDR5 9.2.3.2. Specific Pin Connection Requirements 9.2.3.3. Command and Address Signals 9.2.3.4. Clock Signals
9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP x
9.2.4.1. Address and Command Pin Placement for LPDDR5 9.2.4.2. LPDDR5 Data Width Mapping 9.2.4.3. LPDDR5 Byte Lane Swapping
9.3. LPDDR5 Layout Design Guidelines x
9.3.1. LPDDR5 PCB Stackup and Design Considerations 9.3.2. LPDDR5 General Design Considerations 9.3.3. LPDDR5 Interface Design Guidelines
9.3.3. LPDDR5 Interface Design Guidelines x
9.3.3.1. LPDDR5 Discrete Component/Memory Down Topology (Single Rank or Dual-Rank) 9.3.3.2. Example of an LPDDR5 Layout on an Intel FPGA Platform Board 9.3.3.3. LPDDR5 Simulation Strategy
10. Agilex™ 5 FPGA EMIF IP – Timing Closure x
10.1. Timing Closure 10.2. Optimizing Timing
10.1. Timing Closure x
10.1.1. Timing Analysis
10.1.1. Timing Analysis x
10.1.1.1. PHY or Core
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
11.1. Interface Standard 11.2. Bank Management Efficiency 11.3. Data Transfer 11.4. Improving Controller Efficiency
11.4. Improving Controller Efficiency x
11.4.1. Frequency of Operation 11.4.2. Series of Reads or Writes
12. Agilex™ 5 FPGA EMIF IP – Debugging x
12.1. Interface Configuration Performance Issues 12.2. Functional Issue Evaluation 12.3. Timing Issue Characteristics 12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 12.5. Debugging with the External Memory Interface Debug Toolkit 12.6. Generating Traffic with the Test Engine IP 12.7. Guidelines for Developing HDL for Traffic Generator 12.8. Guidelines for Traffic Generator Status Check 12.9. Hardware Debugging Guidelines 12.10. Create a Simplified Design that Demonstrates the Same Issue 12.11. Measure Power Distribution Network 12.12. Measure Signal Integrity and Setup and Hold Margin 12.13. Vary Voltage 12.14. Operate at a Lower Speed 12.15. Determine Whether the Issue Exists in Previous Versions of Software 12.16. Determine Whether the Issue Exists in the Current Version of Software 12.17. Try A Different PCB 12.18. Try Other Configurations 12.19. Debugging Checklist 12.20. Categorizing Hardware Issues 12.21. Signal Integrity Issues 12.22. Characteristics of Signal Integrity Issues 12.23. Evaluating Signal Integrity Issues 12.24. Skew 12.25. Crosstalk 12.26. Power System 12.27. Clock Signals 12.28. Address and Command Signals 12.29. Read Data Valid Window and Eye Diagram 12.30. Write Data Valid Window and Eye Diagram 12.31. Hardware and Calibration Issues 12.32. Memory Timing Parameter Evaluation 12.33. Verify that the Board Has the Correct Memory Component or DIMM Installed
12.1. Interface Configuration Performance Issues x
12.1.1. Interface Configuration Bottleneck and Efficiency Issues
12.2. Functional Issue Evaluation x
12.2.1. Altera IP Memory Model 12.2.2. Vendor Memory Model 12.2.3. Transcript Window Messages
12.3. Timing Issue Characteristics x
12.3.1. Evaluating FPGA Timing Issues 12.3.2. Evaluating External Memory Interface Timing Issues
12.5. Debugging with the External Memory Interface Debug Toolkit x
12.5.1. Prerequisites for Using the EMIF Debug Toolkit 12.5.2. Configuring a Design to Use the Debug Toolkit 12.5.3. Launching the EMIF Debug Toolkit 12.5.4. Using the EMIF Debug Toolkit
12.5.2. Configuring a Design to Use the Debug Toolkit x
12.5.2.1. Generating a Design Example with the Debug Toolkit
12.5.4. Using the EMIF Debug Toolkit x
12.5.4.1. Running Re-Calibration 12.5.4.2. Running the Test Engine
12.8. Guidelines for Traffic Generator Status Check x
12.8.1. Status Check Using the Signal Tap Logic Analyzer 12.8.2. Exporting the Status Interface to the Top-Level Design
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

9.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions

Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 197.  Group: Configuration Save
Display Name Description
Configuration Filepath

Filepath to Save to (.qprs extension)

(Identifier: MEM_CONFIG_FILE_QPRS)
Table 198.  Group: High-Level Parameters
Display Name Description
Memory Format

Specifies the packaging format of the memory device

(Identifier: MEM_FORMAT)
Memory WCK Frequency for this FSP

Specifies the Write Clock Frequency for this Frequency Set Point

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FQD_FREQ_MHZ)
Number of Channels

Number of channels

(Identifier: MEM_NUM_CHANNELS)
Memory Ranks

Total number of physical ranks in the interface

(Identifier: MEM_NUM_RANKS)
Number of Components Per Rank

Number of components per rank

(Identifier: MEM_COMPS_PER_RANK)
Density of Each Memory Die

Specifies the density of the memory die in Gb

(Identifier: LPDDR5_MEM_DEVICE_DENSITY_GBITS)
Write Link ECC

Enables Write Link ECC for this Frequency Set Point

(Identifier: LPDDR5_MEM_DEVICE_WR_LINK_ECC_EN_FQD)
Read Link ECC

Enables Read Link ECC for this Frequency Set Point

(Identifier: LPDDR5_MEM_DEVICE_RD_LINK_ECC_EN_FQD)
Enable Write Data Bus Inversion

Enables Write Data Bus Inversion

(Identifier: LPDDR5_MEM_DEVICE_WR_DBI_EN)
Enable Read Data Bus Inversion

Enables Read Data Bus Inversion. For future expansion, feature not currently supported.

(Identifier: LPDDR5_MEM_DEVICE_RD_DBI_EN)
Enable Data Mask

Enables Data Masking for write operations

(Identifier: LPDDR5_MEM_DEVICE_DM_EN)
Note: The current version of the Agilex™ 5 EMIF IP does not support Write Link ECC or Read Link ECC. Do not enable Write Link ECC or Read Link ECC when generating LPDDR5 memory presets.
Table 199.  Group: Memory Interface Parameters / Data Bus
Display Name Description
DQ Width per DRAM Component

Specifies the DQ width of each LPDDR5 DRAM component. As byte mode is not supported, this value is always 16. To form x32 LP5 interfaces, select 2 components per rank at the EMIF IP level.

(Identifier: LPDDR5_MEM_DEVICE_DQ_WIDTH)
Total DQ Width Per Channel

Total DQ Width Per Channel. For LPDDR5 packages, this is the product of the per-DRAM DQ Width and Number of Individual DRAM Components per Rank.

(Identifier: LPDDR5_MEM_DEVICE_TOTAL_DQ_WIDTH_PER_CHANNEL)
Burst Length

Burst Length

(Identifier: LPDDR5_MEM_DEVICE_BURST_LENGTH)
Table 200.  Group: Memory Interface Parameters / Device Topology
Display Name Description
Device Row Address Width

Specifies the row address width of this LPDDR5 DRAM component. This value is auto-derived from the specified component density.

(Identifier: LPDDR5_MEM_DEVICE_ROW_ADDR_WIDTH)
Device Maximum Bank Address Width

Specifies the maximum bank address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_MAX_BA_WIDTH)
Device Maximum Bank Group Address Width

Specifies the maximum bank group address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_MAX_BG_WIDTH)
Device Column Address Width

Specifies the column address width of this LPDDR5 DRAM component. This value is fixed for all component densities as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_COL_ADDR_WIDTH)
Device Burst Address Width

Specifies the burst address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR5_MEM_DEVICE_BURST_ADDR_WIDTH)
Table 201.  Group: Memory Timing Parameters / Timing Parameters
Display Name Description
Memory Speedbin

Maximum Data Rate for which this memory device is rated for

(Identifier: LPDDR5_MEM_DEVICE_SPEEDBIN)
Memory Write Latency Set

Selects the Write Latency Set for this device. Selection affects auto-calculation of Write Latency.

(Identifier: LPDDR5_MEM_DEVICE_WLS)
Memory Read Latency

Read Latency of the memory device for this Frequency Set Point in clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_CL_CYC_FQD)
Memory Write Latency

Write Latency of the memory device for this Frequency Set Point in clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_CWL_CYC_FQD)
Table 202.  Group: Memory Timing Parameters / Pre- and Post-Amble Options
Display Name Description
Read Postamble Mode

RDQS Postamble Mode for this Frequency Set Point

(Identifier: LPDDR5_MEM_DEVICE_RDQS_PST_MODE_FQD)
Read Preamble Cycles

RDQS Preamble Length

(Identifier: LPDDR5_MEM_DEVICE_RD_PREAMBLE_CYC)
Read Postamble Cycles

RDQS Postamble Length

(Identifier: LPDDR5_MEM_DEVICE_RD_POSTAMBLE_CYC)
Write Postamble Cycles

WCK Postamble Length

(Identifier: LPDDR5_MEM_DEVICE_WR_POSTAMBLE_CYC)
Table 203.  Group: Memory Timing Parameters / Advanced Timing Parameters
Display Name Description
Min Number of Refs Reqd

Minimum Number of Refreshes Required

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_MINNUMREFSREQ)
tRCD

RAS-to-CAS Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRCD_NS)
tRPab

All-Bank Precharge Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRPAB_NS)
tRPpb

Per-Bank Precharge Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRPPB_NS)
tRAS

Row Active Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRAS_NS)
tRAS_Max

Maximum Row Active Time in us

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRAS_MAX_US)
tWR

Write Recovery Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWR_NS)
tRRD_L

RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Long) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRRD_L_NS)
tRRD_S

RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time (Short) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRRD_S_NS)
tFAW

Four-bank ACTIVE window time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TFAW_NS)
tRBTP

Read Burst End to Precharge Command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRBTP_NS)
tWTR_S

Write-to-Read Delay (Short) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWTR_S_NS)
tWTR_L

Write-to-Read Delay (Long) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TWTR_L_NS)
tPPD

Precharge-to-Precharge Delay Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPPD_NS)
tRC

Activate-to-Activate command period (same bank) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRC_NS)
tZQLAT

ZQCAL Latch Quiet Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TZQLAT_NS)
tPW_RESET

Min RESET_n low time for Reset Initialization with Stable Power Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPW_RESET_NS)
tERQE

Enhanced RDQS Toggle Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TERQE_NS)
tERQX

Enhanced RDQS Toggle Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TERQX_NS)
tRDQE_OD

ODT-disable from Enhanced RDQS Toggle Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQE_OD_NS)
tRDQX_OD

ODT-enable from Enhanced RDQS Toggle Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQX_OD_NS)
tRDQSTFE

Read/Write-based RDQS_t Training Mode Entry Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQSTFE_NS)
tRDQSTFX

Read/Write-based RDQS_t Training Mode Exit Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRDQSTFX_NS)
tCCDMW

CAS-to-CAS Delay for Masked Write in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCCDMW_NS)
tREFW

Refresh Window in ms

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TREFW_MS)
tREFI

Refresh Interval Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TREFI_NS)
tRFCab

All-Bank Refresh Cycle Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRFCAB_NS)
tRFCpb

Per-Bank Refresh Cycle Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TRFCPB_NS)
tpbR2pbR

Per-Bank Refresh to Per-Bank Refresh minimum interval time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPBR2PBR_NS)
tpbR2ACT

Per-Bank Refresh to Activate minimum interval time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TPBR2ACT_NS)
tCKCSH

Valid Clock Requirement before CS goes High (Power-Down AC Timings) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCKCSH_NS)
tCMDPD

Delay from valid command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCMDPD_NS)
tXP

Exit Power-Down to next valid command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TXP_NS)
tCSH

Minimum CS High Pulse Width at Power Down Exit in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSH_NS)
tCSLCK

Valid Clock Requirement after Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSLCK_NS)
tCSPD

Delay time from Power Down Entry to CS going High in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TCSPD_NS)
tMRWPD

Delay from MRW Command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRWPD_NS)
tZQPD

Delay from ZQ Calibration Start/Latch Command to Power Down Entry in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TZQPD_NS)
tESPD

Delay time from Self-Refresh Entry command to Power Down Entry commmand in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TESPD_NS)
tSR

Minimum Self-Refresh Time (Entry to Exit) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TSR_NS)
tXSR

Exit Self-Refresh time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TXSR_NS)
tMRR

Mode Register Read Command Period in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRR_NS)
tMRW

Mode Register Write Command Period in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRW_NS)
tMRD

Mode Register Set Command Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TMRD_NS)
tOSCO

Delay time from Stop WCK2DQI/WCK2DQO Interval Oscillator Command to Mode Register Readout time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TOSCO_NS)
tDQSCK_MAX

Maximum additional delay needed for tDQSCK in Picoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TDQSCK_MAX_PS)
tDQSCK_MIN

Minimum additional delay needed for tDQSCK in Picoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR5_MEM_DEVICE_TDQSCK_MIN_PS)
Level Two Title