External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

8.2.3.2. Specific Pin Connection Requirements

PLL

  • For LPDDR4, you must constrain the PLL reference clock to the address and command lanes only.
  • You must constrain differential reference clocks to pin indices 10 and 11 in lane 2 when placing command address pins in lane 3 and lane 2.
  • The sharing of PLL reference clocks across multiple LPDDR4 interfaces is permitted within an I/O bank.
Note: Agilex™ 5 FPGAs do not support single-ended I/O PLL reference clocks for EMIF IP.

OCT

  • For LPDDR4, you must constrain the RZQ pin to the address and command lanes only.
  • You must constrain RZQ to pin index 2 in lane 3 when placing command address pins in lane 3 and lane 2.
  • The sharing of RZQ pins across multiple LPDDR4 interfaces is permitted within an I/O bank.

DQS/DQ/DM

For LPDDR4 x8 DQS grouping, the following rules apply:

  • You may use pin indices 0, 1, 2, 3, 8, 9, 10, and 11 within a lane for DQ mode pins only.
  • You must use pin index 4 for the DQS_p pin only.
  • You must use pin index 5 for the DQS_n pin only.
  • You must ensure that pin index 7 remains unused. Pin index 7 is not available for use as a general purpose I/O.
  • You must use pin index 6 for the DM pin only.
  • The following table indicates the pin index within an I/O lane and the DQS, DQ and DM pin placement:
    pin0 pin1 pin2 pin3 pin4 pin5 pin6 pin7 pin8 pin9 pin10 pin11
    DQ DQ DQ DQ DQSp DQSn DM unused DQ DQ DQ DQ