External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Agilex™ 5 FPGA EMIF IP - DDR5 Support 8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 10. Agilex™ 5 FPGA EMIF IP – Timing Closure 11. Agilex™ 5 FPGA EMIF IP – Controller Optimization 12. Agilex™ 5 FPGA EMIF IP – Debugging 13. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Lockstep Configuration 3.2.3.2. Pin Placement 3.2.3.3. HSIO Sub-Bank Usage
3.3. Agilex™ 5 EMIF Sequencer x
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions x
3.3.1.1. Mailbox Supported Commands 3.3.1.2. Mailbox Command Definitions
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. Agilex 5 EMIF IP Interfaces for DDR4 4.2. Agilex 5 EMIF IP Interfaces for DDR5 4.3. Agilex 5 EMIF IP Interfaces for LPDDR4 4.4. Agilex 5 EMIF IP Interfaces for LPDDR5 4.5. Agilex 5 EMIF IP Interfaces for the EMIF Calibration Component
4.1. Agilex 5 EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF IP 4.1.2. core_init_n for EMIF IP 4.1.3. usr_async_clk for EMIF IP 4.1.4. usr_clk for EMIF IP 4.1.5. usr_rst_n for EMIF IP 4.1.6. s0_axi4 for EMIF IP 4.1.7. mem for EMIF IP 4.1.8. oct for EMIF IP
4.2. Agilex 5 EMIF IP Interfaces for DDR5 x
4.2.1. ref_clk for EMIF IP 4.2.2. core_init_n for EMIF IP 4.2.3. usr_async_clk for EMIF IP 4.2.4. usr_clk for EMIF IP 4.2.5. usr_rst_n for EMIF IP 4.2.6. s0_axi4 for EMIF IP 4.2.7. mem for EMIF IP 4.2.8. i3c for EMIF IP 4.2.9. mem_lbd for EMIF IP 4.2.10. mem_lbs for EMIF IP 4.2.11. oct for EMIF IP
4.3. Agilex 5 EMIF IP Interfaces for LPDDR4 x
4.3.1. ref_clk for EMIF IP 4.3.2. core_init_n for EMIF IP 4.3.3. usr_async_clk for EMIF IP 4.3.4. usr_clk for EMIF IP 4.3.5. usr_rst_n for EMIF IP 4.3.6. s0_axi4 for EMIF IP 4.3.7. mem for EMIF IP 4.3.8. oct for EMIF IP
4.4. Agilex 5 EMIF IP Interfaces for LPDDR5 x
4.4.1. ref_clk for EMIF IP 4.4.2. core_init_n for EMIF IP 4.4.3. usr_async_clk for EMIF IP 4.4.4. usr_clk for EMIF IP 4.4.5. usr_rst_n for EMIF IP 4.4.6. s0_axi4 for EMIF IP 4.4.7. mem for EMIF IP 4.4.8. oct for EMIF IP
4.5. Agilex 5 EMIF IP Interfaces for the EMIF Calibration Component x
4.5.1. s0_axi4lite_clk for EMIF IP Calibration Component 4.5.2. s0_axi4lite_rst_n for EMIF IP Calibration Component 4.5.3. s0_axil for EMIF IP Calibration Component
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR4 6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.3. Agilex™ 5 EMIF Pin Swapping Guidelines 6.4. DDR4 Layout Design Guidelines
6.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR4 x
6.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for DDR4 6.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions 6.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.1. Agilex™ 5 FPGA EMIF IP Resources 6.2.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 6.2.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP
6.2.1. Agilex™ 5 FPGA EMIF IP Resources x
6.2.1.1. OCT 6.2.1.2. PLL
6.2.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
6.2.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.2.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.2.1.1. Agilex™ 5 FPGA EMIF IP Interface Pins 6.2.2.1.2. Estimating Pin Requirements 6.2.2.1.3. Maximum Number of Interfaces
6.2.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP x
6.2.3.1. Address and Command Pin Placement for DDR4 6.2.3.2. DDR4 Data Width Mapping 6.2.3.3. General Guidelines 6.2.3.4. x4 DIMM Implementation 6.2.3.5. Specific Pin Connection Requirements 6.2.3.6. Command and Address Signals 6.2.3.7. Clock Signals 6.2.3.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.3.1. DDR4 Byte Lane Swapping 6.3.2. DDR4 Address and Command and CLK Lane 6.3.3. DDR4 Interface x8 Data Lane 6.3.4. DDR4 Interface x4 Data Lane
6.4. DDR4 Layout Design Guidelines x
6.4.1. DDR4 PCB Stackup and Design Considerations 6.4.2. DDR4 General Design Considerations 6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies
6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies x
6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology 6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations 6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations 6.4.3.6. DDR4 Simulation Strategy
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support x
7.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR5 7.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
7.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR5 x
7.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for DDR5 7.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions 7.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
7.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 7.2.2. Agilex™ 5 FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 7.2.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP 7.2.5. Agilex™ 5 EMIF Pin Swapping Guidelines
7.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. DIMM Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Agilex™ 5 FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
7.2.3.1. General Guidelines - DDR5 7.2.3.2. x4 DIMM Implementation 7.2.3.3. Specific Pin Connection Requirements 7.2.3.4. Command and Address Signals 7.2.3.5. Clock Signals 7.2.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.2.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP x
7.2.4.1. Address and Command Pin Placement for DDR5 7.2.4.2. DDR5 Data Width Mapping
7.2.5. Agilex™ 5 EMIF Pin Swapping Guidelines x
7.2.5.1. DDR5 Byte Lane Swapping 7.2.5.2. DDR5 Address and Command and CLK Lane 7.2.5.3. DDR5 Interface x8 Data Lane 7.2.5.4. DDR5 Interface x4 Data Lane 7.2.5.5. Pin Swizzling
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
8.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR4 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR4 Layout Design Guidelines
8.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR4 x
8.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for LPDDR4 8.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR4) Parameter Descriptions 8.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR4 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals 8.2.3.5. Address and Command Pin Placement for LPDDR4 8.2.3.6. LPDDR4 Data Width Mapping 8.2.3.7. Pin Swapping Guidelines
8.3. LPDDR4 Layout Design Guidelines x
8.3.1. LPDDR4 PCB Stackup and Design Considerations 8.3.2. LPDDR4 General Design Considerations 8.3.3. LPDDR4 Interface Design Guidelines
8.3.3. LPDDR4 Interface Design Guidelines x
8.3.3.1. LPDDR4 Discrete Component/Memory Down Topology (up to 32 bits interface) 8.3.3.2. LPDDR4 Simulation Strategy
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
9.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR5 9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 9.3. LPDDR5 Layout Design Guidelines
9.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR5 x
9.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for LPDDR5 9.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions 9.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 9.2.2. Agilex™ 5 FPGA EMIF IP Resources 9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
9.2.1.1. Estimating Pin Requirements 9.2.1.2. LPDDR5 Component Options 9.2.1.3. Maximum Number of Interfaces
9.2.2. Agilex™ 5 FPGA EMIF IP Resources x
9.2.2.1. OCT 9.2.2.2. PLL
9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
9.2.3.1. General Guidelines - LPDDR5 9.2.3.2. Specific Pin Connection Requirements 9.2.3.3. Command and Address Signals 9.2.3.4. Clock Signals
9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP x
9.2.4.1. Address and Command Pin Placement for LPDDR5 9.2.4.2. LPDDR5 Data Width Mapping 9.2.4.3. LPDDR5 Byte Lane Swapping
9.3. LPDDR5 Layout Design Guidelines x
9.3.1. LPDDR5 PCB Stackup and Design Considerations 9.3.2. LPDDR5 General Design Considerations 9.3.3. LPDDR5 Interface Design Guidelines
9.3.3. LPDDR5 Interface Design Guidelines x
9.3.3.1. LPDDR5 Discrete Component/Memory Down Topology (Single Rank or Dual-Rank) 9.3.3.2. Example of an LPDDR5 Layout on an Intel FPGA Platform Board 9.3.3.3. LPDDR5 Simulation Strategy
10. Agilex™ 5 FPGA EMIF IP – Timing Closure x
10.1. Timing Closure 10.2. Optimizing Timing
10.1. Timing Closure x
10.1.1. Timing Analysis
10.1.1. Timing Analysis x
10.1.1.1. PHY or Core
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
11.1. Interface Standard 11.2. Bank Management Efficiency 11.3. Data Transfer 11.4. Improving Controller Efficiency
11.4. Improving Controller Efficiency x
11.4.1. Frequency of Operation 11.4.2. Series of Reads or Writes
12. Agilex™ 5 FPGA EMIF IP – Debugging x
12.1. Interface Configuration Performance Issues 12.2. Functional Issue Evaluation 12.3. Timing Issue Characteristics 12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 12.5. Debugging with the External Memory Interface Debug Toolkit 12.6. Generating Traffic with the Test Engine IP 12.7. Guidelines for Developing HDL for Traffic Generator 12.8. Guidelines for Traffic Generator Status Check 12.9. Hardware Debugging Guidelines 12.10. Create a Simplified Design that Demonstrates the Same Issue 12.11. Measure Power Distribution Network 12.12. Measure Signal Integrity and Setup and Hold Margin 12.13. Vary Voltage 12.14. Operate at a Lower Speed 12.15. Determine Whether the Issue Exists in Previous Versions of Software 12.16. Determine Whether the Issue Exists in the Current Version of Software 12.17. Try A Different PCB 12.18. Try Other Configurations 12.19. Debugging Checklist 12.20. Categorizing Hardware Issues 12.21. Signal Integrity Issues 12.22. Characteristics of Signal Integrity Issues 12.23. Evaluating Signal Integrity Issues 12.24. Skew 12.25. Crosstalk 12.26. Power System 12.27. Clock Signals 12.28. Address and Command Signals 12.29. Read Data Valid Window and Eye Diagram 12.30. Write Data Valid Window and Eye Diagram 12.31. Hardware and Calibration Issues 12.32. Memory Timing Parameter Evaluation 12.33. Verify that the Board Has the Correct Memory Component or DIMM Installed
12.1. Interface Configuration Performance Issues x
12.1.1. Interface Configuration Bottleneck and Efficiency Issues
12.2. Functional Issue Evaluation x
12.2.1. Altera IP Memory Model 12.2.2. Vendor Memory Model 12.2.3. Transcript Window Messages
12.3. Timing Issue Characteristics x
12.3.1. Evaluating FPGA Timing Issues 12.3.2. Evaluating External Memory Interface Timing Issues
12.5. Debugging with the External Memory Interface Debug Toolkit x
12.5.1. Prerequisites for Using the EMIF Debug Toolkit 12.5.2. Configuring a Design to Use the Debug Toolkit 12.5.3. Launching the EMIF Debug Toolkit 12.5.4. Using the EMIF Debug Toolkit
12.5.2. Configuring a Design to Use the Debug Toolkit x
12.5.2.1. Generating a Design Example with the Debug Toolkit
12.5.4. Using the EMIF Debug Toolkit x
12.5.4.1. Running Re-Calibration 12.5.4.2. Running the Test Engine
12.8. Guidelines for Traffic Generator Status Check x
12.8.1. Status Check Using the Signal Tap Logic Analyzer 12.8.2. Exporting the Status Interface to the Top-Level Design
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

3.3.1.2. Mailbox Command Definitions

Table 23.  CMD_TYPE Definition
CMD_TYPE Value Description
CMD_NOP 0x00 No operation command.
CMD_GET_SYS_INFO 0x01 Retrieving information about the IO96B configuration.
CMD_GET_MEM_INFO 0x02 Retrieving information about the memory interface operation.
CMD_TRIG_CONTROLLER_OP 0x04 Triggering memory controller-related operations.
CMD_TRIG_MEM_CAL_OP 0x05 Triggering calibration events.
Table 24.  CMD_REQ Definition
Bit Name Description Access Reset
[31:29] CMD_TARGET_IP_TYPE Indicates the type of IP, as follows:
  • 0x0 – Not used.
  • 0x1 – Primary MC of primary IO96B.
  • 0x2 – Secondary MC of primary IO96B.
  • 0x3 – Primary MC of secondary IO96B.
  • 0x4 – Secondary MC of secondary IO96B.
 Read-Write 0x0
[28:24] CMD_TARGET_IP_INSTANCE_ID IP identifier. Read-Write 0x00
[23:16] CMD_TYPE The type of command that the user wants the firmware to perform. Read-Write 0x00
[15:0] CMD_OPCODE The opcode of the command that the user wants the firmware to perform. Read-Write 0x00
Table 25.  CMD_TARGET_IP_TYPE Definition
Multi-channel/Lockstep Configurations CMD_TARGET_IP_TYPE
1 – Primary MC, Primary IO96B 2 – Secondary MC, Primary IO96B 3 – Primary MC, Secondary IO96B 4 – Secondary MC, Secondary IO96B
LPDDR4/5 2CHx16 CH1 CH2    
LPDDR4/5 4CHx16 CH1 CH2 CH3 CH4
DDR5 2CHx16 CH1 CH2    
DDR5 2CHx32 CH1   CH2  
DDR5 x40 lockstep CH1 *    
DDR4 x40 lockstep CH1 *    
DDR4 x64, x72 lockstep CH1 * * *
Note: * These controllers are used but have no (or limited) mailbox features due to limited lockstep capabilities.
Table 26.  Command Definitions
CMD_REQ Description

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <UNUSED>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <UNUSED>

CMD_REQ [23:16]: CMD_TYPE = CMD_GET_SYS_INFO

CMD_REQ [15:0]: CMD_OPCODE = GET_MEM_INTF_INFO

Command to get the memory interface IP type and instance ID of all the IPs in the IO96B.

[Inputs] N/A

[Outputs[KSH1] [VCV2] [KSH3] ]

CMD_RESPONSE_DATA_SHORT [1:0]: NUM_USED_MEM_INTF

Number of memory interfaces instantiated.

CMD_RESPONSE_DATA_0 [31:29]: INTF_0_IP_TYPE Indicates the type of IP for Interface 0:

0x0 – Not used

0x1 – EMIF

CMD_RESPONSE_DATA_0 [28:24]: INTF_0_INSTANCE_ID IP identifier for Interface 0.

CMD_RESPONSE_DATA_1 [31:29]: INTF_1_IP_TYPE

Indicates the type of IP for Interface 1:

0x0 – Not used

0x1 – EMIF

CMD_RESPONSE_DATA_1 [28:24]: INTF_1_INSTANCE_ID

IP identifier for Interface 1.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_GET_MEM_INFO

CMD_REQ [15:0]: CMD_OPCODE = GET_MEM_TECHNOLOGY

Command to get the memory technology of the memory interface specified using the instance ID.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT [2:0]: MEM_TECHNOLOGY

Reports the memory type as below:

0x0 = DDR4, 0x1 = DDR5, 0x2 = DDR5_RDIMM, 0x3 = LPDDR4, 0x4 = LPDDR5, 0x5 = QDRIV

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_GET_MEM_INFO

CMD_REQ [15:0]: CMD_OPCODE = GET_MEMCLK_FREQ_KHZ

Command to get the memory clock frequency of the memory interface specified using the instance ID.

[Inputs]

CMD_PARAM_0 [1:0]: FREQUENCY_SET_POINT

Get clock frequency for the specified frequency set point.

0x0 = Frequency set point 0

0x1 = Frequency set point 1

0x2 = Frequency set point 2

CMD_PARAM_0 [2:2]: USE_CURRENT_FSP

Get clock frequency for the current frequency set point.

0x0 = Use FSP specified using FREQUENCY_SET_POINT.

0x1 = Use current FSP

[Outputs]

CMD_RESPONSE_DATA_0: DRAM_CLK_FREQ_KHZ

Reports the memory clock frequency in KHz for the input frequency set point.

[Errors]

CMD_RESPONSE_STATUS - STATUS_CMD_RESPONSE_ERROR:

000 – No errors

111 – The FSP specified using FREQUENCY_SET_POINT is not defined.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_GET_MEM_INFO

CMD_REQ [15:0]: CMD_OPCODE = GET_MEM_WIDTH_INFO

Command to get the memory width information of the memory interface specified using the instance ID.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_0 [7:0]: DQ_WIDTH

CMD_RESPONSE_DATA_0 [15:8]: CS_WIDTH

CMD_RESPONSE_DATA_0 [23:16]: C_WIDTH

CMD_RESPONSE_DATA_1 [7:0]: TOTAL_MEM_CAPACITY

Memory device capacity in Gb (gigabits) calculated as:

CAPACITY = (DQ_WIDTH / DEVICE_WIDTH) * DEVICE_DENSITY

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_ENABLE_SET

Command to enable different ECC modes for the memory interface specified using the instance ID.

[Inputs]

CMD_PARAM_0 [1:0]: ECC_ENABLE

Set the current ECC error reporting (single-bit and double-bit errors) and correcting (single-bit errors) that is enabled.

’b00 = ECC is disabled. Data is written to the memory without ECC values, and data is returned to the user interface without being verified for accuracy.

’b01 = ECC is enabled, but without detection or correction.

’b10 = ECC is enabled with detection, but correction is not supported. When an error is found on a read operation, ECC reporting parameters are updated for read commands. Erroneous data is returned to the user on read commands and written to the memory on write commands.

’b11 = ECC is enabled with detection and correction. When an error is found on a read operation, the ECC reporting parameters are updated for read commands. Single bit errors are corrected automatically by the controller in both read and write commands.

CMD_PARAM_0[2:2]: ECC_TYPE

‘b0 = Out-of-Band ECC

‘b1 =In-line ECC

[Outputs] N/A

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_ENABLE_STATUS

Command to get the ECC enable status of the memory interface specified using the instance ID.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT [1:0]: ECC_ENABLE

Reports the current ECC error reporting (single-bit and double-bit errors) and correcting (single-bit errors) that is enabled.

’b00 = ECC is disabled. Data is written to the memory without ECC values, and data is returned to the user interface without being verified for accuracy.

’b01 = ECC is enabled, but without detection or correction.

’b10 = ECC is enabled with detection, but correction is not supported. When an error is found on a read operation, ECC reporting parameters are updated for read commands. Erroneous data is returned to the user on read commands and written to the memory on write commands.

’b11 = ECC is enabled with detection and correction. When an error is found on a read operation, the ECC reporting parameters are updated for read commands. Single bit errors are corrected automatically by the controller in both read and write commands.

CMD_RESPONSE_DATA_SHORT[2:2]:

ECC_TYPE

‘b0 = Out-of-Band ECC

‘b1 =In-line ECC

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_INTERRUPT_STATUS

Command to get status of ECC interrupts for the memory interface specified using the instance ID.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_0 [16:0]: ECC_INTERRUPT_STATUS

Reports the interrupts related to the ECC logic.

Bit [8] = An ECC correctable error has been detected in a scrubbing read operation

Bit [7] = The triggered scrub operation has completed.

Bit [6] = One or more ECC writeback commands could not be executed.

Bit [3] = Another un-correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [2] = An un-correctable ECC event has been detected on a read operation.

Bit [1] = Another correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [0] = A correctable ECC event has been detected on a read operation

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_INTERRUPT_ACK

Command to acknowledge and clear the ECC interrupts for the memory interface specified using the instance ID.

[Inputs]

CMD_PARAM_0 [16:0]: ECC_INTERRUPT_ACK

Used to acknowledge and clear the interrupts related to the ECC logic.

Bit [8] = An ECC correctable error has been detected in a scrubbing read operation

Bit [7] = The triggered scrub operation has completed.

Bit [6] = One or more ECC writeback commands could not be executed.

Bit [3] = Another un-correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [2] = An un-correctable ECC event has been detected on a read operation.

Bit [1] = Another correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [0] = A correctable ECC event has been detected on a read operation

[Outputs] N/A

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_INTERRUPT_MASK

Command to set mask for ECC interrupts for the memory interface specified using the instance ID, in order to disable specific ECC interrupts.

[Inputs]

CMD_PARAM_0 [16:0]: ECC_INTERRUPT_MASK

If any bit is set to ’b1 in this parameter, the corresponding interrupt does NOT trigger an interrupt on the top-level EMIF interrupt signal.

Bit [13] = A RMW Read Link ECC double-bit error has been detected

Bit [12] = A Read Link ECC double-bit error has been detected.

Bit [11] = A Read Link ECC single-bit error has been detected.

Bit [10] = A Write Link ECC double-bit error has been detected by the periodic MRR to MR43.

Bit [9] = A Write Link ECC single-bit error has been detected by the periodic MRR to MR43.

Bit [8] = An ECC correctable error has been detected in a scrubbing read operation

Bit [7] = The triggered scrub operation has completed.

Bit [6] = One or more ECC writeback commands could not be executed.

Bit [3] = Another un-correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [2] = An un-correctable ECC event has been detected on a read operation.

Bit [1] = Another correctable ECC event has been detected on a read operation, prior to the initial event being acknowledged.

Bit [0] = A correctable ECC event has been detected on a read operation

[Outputs] N/A

CMD_REQ column is:

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_WRITEBACK_ENABLE

Command to set automatic writing of corrected errors on read operation for the memory interface specified using the instance ID

CMD_PARAM_0 [0:0]: ECC_WRITEBACK_EN

Enables automatic writing of corrected data on single bit correctable errors on read operations. This parameter is only relevant if ECC is enabled with detection and correction (ECC_ENABLE = ’b11). Note: No writebacks will be issued during BIST. ’b0 = Disable. ’b1 = Enable

[Outputs] N/A

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC detection and correction not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_GET_SBE_INFO

Command to get the details on the single-bit (SBE) or correctable errors detected by ECC for the memory interface specified using the instance ID. This command should be called only if all of the following conditions are true:

1. A correctable ECC event occurs.

2. ECC is enabled in the ECC_ENABLE parameter (’b01, ’b10 or ’b11).

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_0 [31:0]: ECC_SBE_INFO_SIZE

Holds the size of the single bit error details. The value of this is 192 bits.

CMD_RESPONSE_DATA_1 [31:0]: ECC_SBE_INFO_PTR

Holds the offset pointer of the single bit error details. The data at the pointer location is as shown below:

OFFSET [0] to OFFSET [1]: ECC_SBE_ADDR [37:0]

Holds the address of the read data that caused a single-bit correctable ECC event. The Controller pads this parameter with zeros for any address bits not used by the controller. Here, the 5th bit of OFFSET [0] has the 37th bit, and the lowest bit of OFFSET [1] has the 0th bit of ECC_SBE_ADDR.

OFFSET [2] to OFFSET [3]: ECC_SBE_DATA [63:0]

Holds the pre-corrected data associated with a single-bit correctable ECC event.

OFFSET [4]: ECC_SBE_ID [6:0]

Holds the source ID associated with a single-bit correctable ECC event. For AXI ports, the source ID is comprised of the Port ID (upper bit/s) and the Requestor ID, where the Requestor ID is the axi0_AWID for write commands or the axi0_ARID for read commands.

OFFSET [5]: ECC_SBE_SYND [7:0]

Holds the syndrome value associated with a single-bit correctable ECC error event. This value indicates which bit of the check code or data was erroneous. Table 7 shows the syndrome corresponding to the single bit errors.

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_GET_DBE_INFO

Command to get the details on the double-bit (DBE) or uncorrectable errors detected by ECC for the memory interface specified using the instance ID. This command should be called only if all of the following conditions are true:

1. An uncorrectable ECC event occurs.

2. ECC is enabled in the ECC_ENABLE parameter (’b01, ’b10 or ’b11.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_0 [31:0]: ECC_DBE_INFO_SIZE

Holds the size of the double bit error details. The value of this is 192 bits.

CMD_RESPONSE_DATA_1 [31:0]: ECC_DBE_INFO_PTR

Holds the offset pointer of the double bit error details. The data at the pointer location is as shown below:

OFFSET [0] to OFFSET [1]: ECC_DBE_ADDR [37:0]

Holds the address of the read data that caused a double-bit uncorrectable ECC event. The Controller pads this parameter with zeros for any address bits not used by the controller. Here, the 5th bit of OFFSET [0] has the 37th bit, and the lowest bit of OFFSET [1] has the 0th bit of ECC_SBE_ADDR.

OFFSET [2] to OFFSET [3]: ECC_DBE_DATA [63:0]

Holds the data associated with a double-bit uncorrectable ECC event.

OFFSET [4]: ECC_DBE_ID [6:0]

Holds the source ID associated with a double-bit uncorrectable ECC event. For AXI ports, the source ID is comprised of the Port ID (upper bit/s) and the Requestor ID, where the Requestor ID is the axi0_AWID for write commands or the axi0_ARID for read commands.

OFFSET [5]: ECC_DBE_SYND [7:0]

Holds the syndrome bits associated with a double-bit un-correctable ECC error event. This controller can indicate that only 2 bits of the data and/or check code are erroneous but can not identify which bits. Table 7 shows the syndrome corresponding to the single bit errors.

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_SCRUB_IN_PROGRESS_STATUS

Command to check if the ECC scrub is in-progress for the memory interface specified using the instance ID.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: ECC_SCRUB_IN_PROGRESS

Reports the scrubbing operation status. This parameter is read-only. ’b0 = Not actively performing a scrubbing operation. ’b1 = The Controller is in the process of performing a scrubbing operation.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_SCRUB_MODE_0_START

Command to start ECC scrub in mode 0 where scrub is performed at regular intervals for the memory interface specified using the instance ID.

[Inputs]

CMD_PARAM_0 [15:0]: ECC_SCRUB_INTERVAL

Sets the minimum interval between two ECC scrubbing commands, in number of controller clock cycles. The controller clock is based on the Controller’s operating frequency. Clearing this parameter to 0x0000 disables interval operation.

CMD_PARAM_1 [11:0]: ECC_SCRUB_LEN

Defines the length (in bytes) of the ECC scrubbing read command that the controller issues. This value must be an integer multiple of the memory burst length, and the lowest 3 bits of this parameter must be cleared to ’b0.

CMD_PARAM_2 [0:0]: ECC_SCRUB_FULL_MEM

Defines whether to perform ECC scrub on full memory or on the specified address range.

‘b0 – ECC scrub performed on address range specified using ECC_SCRUB_START_ADDR and ECC_SCRUB_END_ADDR

‘b1 – ECC scrub performed on full memory address range

CMD_PARAM_3 [31:0]: ECC_SCRUB_START_ADDR [31:0]

CMD_PARAM_4 [5:0]: ECC_SCRUB_START_ADDR [36:32]

Defines the starting address from where scrubbing operations begin. This value must be less than or equal to the value programmed into the ECC_SCRUB_END_ADDR parameter. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

CMD_PARAM_5 [31:0]: ECC_SCRUB_END_ADDR [31:0]

CMD_PARAM_6 [5:0]: ECC_SCRUB_END_ADDR [36:32]

Defines the ending address at which scrubbing operations wrap around to the start address. This parameter must be programmed to a non-zero value for the scrubbing logic to operate. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: ECC_SCRUB_INITIATED

‘b1 – ECC scrub initiated successfully

‘b0 – ECC scrub initiation failed

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_SCRUB_MODE_1_START

Command to start ECC scrub in mode 1 where scrub is performed when the controller is idle for the memory interface specified using the instance ID.

[Inputs]

CMD_PARAM_0 [15:0]: ECC_SCRUB_IDLE_CNT

Defines the number of controller clock cycles that the scrubbing engine waits in the Controller’s idle state before starting scrubbing operations. The Controller is considered idle when the command queue is empty. When this condition is detected, an internal counter loads with the value programmed in this parameter and count down on each controller clock. When the counter expires, either the scrubbing operation begins or the next address is tested. The controller clock is based on the Controller’s operating frequency. Clearing this parameter to 0x0000 disables idle operation.

CMD_PARAM_1 [11:0]: ECC_SCRUB_LEN

Defines the length (in bytes) of the ECC scrubbing read command that the controller issues. This value must be an integer multiple of the memory burst length, and the lowest 3 bits of this parameter must be cleared to ’b0.

CMD_PARAM_2 [0:0]: ECC_SCRUB_FULL_MEM

Defines whether to perform ECC scrub on full memory or on the specified address range.

‘b0 – ECC scrub performed on address range specified using ECC_SCRUB_START_ADDR and ECC_SCRUB_END_ADDR

‘b1 – ECC scrub performed on full memory address range

CMD_PARAM_3 [31:0]: ECC_SCRUB_START_ADDR [31:0]

CMD_PARAM_4 [5:0]: ECC_SCRUB_START_ADDR [36:32]

Defines the starting address from where scrubbing operations begin. This value must be less than or equal to the value

programmed into the ECC_SCRUB_END_ADDR parameter. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

CMD_PARAM_5 [31:0]: ECC_SCRUB_END_ADDR [31:0]

CMD_PARAM_6 [5:0]: ECC_SCRUB_END_ADDR [36:32]

Defines the ending address at which scrubbing operations wrap around to the start address. This parameter must be programmed to a non-zero value for the scrubbing logic to operate. Only used when ECC_SCRUB_FULL_MEM is ‘b0.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: ECC_SCRUB_INITIATED

‘b1 – ECC scrub initiated successfully

‘b0 – ECC scrub initiation failed

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = ECC_INJECT_ERROR

Command to force a specific check code to be written into memory interface specified using the instance ID for diagnostic purposes or for flagging a particular memory address as erroneous for future accesses. The procedure is as follows:

  1. Set the ECC_ENABLE parameter to enable detection (’b1x).
  2. Ensure that no writes to the controller are pending.
  3. Send ECC_INJECT_ERROR command through mailbox setting the ECC_XOR_CHECK_BITS input parameter. Use the syndromes to program the ECC_XOR_CHECK_BITS parameter. Each byte of the ECC_XOR_CHECK_BITS parameter controls the ECC event forcing for a separate user-word space. For example, setting a value of 0xF4 as ECC_XOR_CHECK_BITS will result in the check bits to be updated and written to the memory such that it flags a single-bit correctable error on bit [0] of the user-word on subsequent access of the same address.
  4. Execute a write command for an aligned user word. The controller will XOR the ECC_XOR_CHECK_BITS parameter with the generated checksum bits from the word written to the memory. The next read command to the same address will force the ECC error.
  5. Depending on the programming of the ECC_XOR_CHECK_BITS parameter, a single bit, double bit or multi-bit ECC error will occur. For single bit and double bit errors, the appropriate bit in the ECC_INTERRUPT_STATUS parameter will be set to ’b1 and the ECC error signature parameters will be filled with the relevant information.

[Inputs]

CMD_PARAM_0 [31:0]: ECC_XOR_CHECK_BITS

The check bits generated by the next write operation will be XOR’ed with this parameter. The result will be written into memory as the new check value.

ECC_XOR_CHECK_BITS [31:24] maps to user word [255:192]

ECC_XOR_CHECK_BITS [23:16] maps to user word [191:128]

ECC_XOR_CHECK_BITS [15:8] maps to user word [127:64]

ECC_XOR_CHECK_BITS [7:0] maps to user word [63:0]

[Outputs] N/A

[Command-Specific Errors]

‘b000 – No errors

‘b001 – ECC detection not enabled

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_STANDARD_MODE_START

Command to initiate Original MOVI1 3N BIST algorithm for data checking for the memory interface specified using the instance ID. This command MUST be followed by BIST_RESULTS_STATUS to get the results of the BIST operation and resume normal operation of the memory controller.

[Inputs]

CMD_PARAM_0 [5:0]: BIST_ADDR_SPACE [5:0]

Used in BIST data checking to define the address space in bytes from 0 to 2addr_space that the BIST logic checks. As an example, if the addr_space parameter was programmed to 0x1c, then the BIST logic would check 228 bytes = 256 MBytes. Note: A BIST test must cover a minimum of 2 bursts. Therefore, the user must program this parameter to a value such that the start address and end address of the BIST test encompass a minimum of 2 bursts. Only used if BIST_FULL_MEM is ‘b0.

CMD_PARAM_0 [6:6]: BIST_FULL_MEM

Defines whether to perform BIST on full memory or on the specified address range.

‘b0 – BIST performed on address range specified using BIST_START_ADDR and BIST_ADDR_SPACE

‘b1 – BIST performed on full memory address range

CMD_PARAM_1 [31:0]: BIST_START_ADDR [31:0]

CMD_PARAM_2 [5:0]: BIST_START_ADDR [36:32]

Used in BIST data checking and memory initialization programming to define the starting address for BIST checking in bytes. Only used if BIST_FULL_MEM is ‘b0.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: BIST_INITIATED

‘b1 – BIST initiated successfully

‘b0 – BIST initiation failed

[Command-Specific Errors]

‘b00 – No errors

‘b01 – A previous command’s saved state not restored. For example, BIST_STANDARD_MODE_START should be followed by BIST_RESULTS_STATUS command to restored saved state and resume normal memory controller operation.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_RESULTS_STATUS

Command to get BIST results for the previously initiated BIST operation for memory interface specified using the instance ID

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: BIST_STATUS

Holds the status of the BIST operation.

’b0 = BIST operation still in progress if previously initiated.

’b1 = BIST operation has been completed.

[Command-Specific Error]

‘b00 – No errors

‘b01 – Could not restore saved state. BIST_STANDARD_MODE_START command MUST be immediately followed by BIST_RESULTS_STATUS to get the results of the BIST operation, restore saved state, and resume normal operation of the memory controller. The populated results, if any, may be invalid.

CMD_RESPONSE_DATA_SHORT [3:3]: BIST_RESULT

Holds the result of the BIST operation. For this BIST mode, the test ends at the first failure, or completely checks the specified data range if no failures are found. This value is valid when BIST_STATUS indicates that the BIST operation has completed.

’b0 = Data check failed. ’b1 = Data check passed.

CMD_RESPONSE_DATA_0 [31:0]: BIST_FAIL_RESULT_SIZE

Holds the size of the BIST failure results. The value of this is 640 bits.

CMD_RESPONSE_DATA_1 [31:0]: BIST_FAIL_RESULT_PTR

Holds the offset pointer of the BIST failure results. The data at the pointer location is as shown below:

OFFSET [0] to OFFSET [8]: BIST_EXP_DATA [287:0]

Holds the expected read data for a BIST data check failure. Here, the highest bit of OFFSET [0] has the 287th bit, and the lowest bit of OFFSET [8] has the 0th bit of BIST_EXP_DATA.

OFFSET [9] to OFFSET [10]: BIST_FAIL_ADDR [37:0]

Holds the actual failing address for a BIST data check failure.

OFFSET [11] to OFFSET [20]: BIST_FAIL_DATA [287:0]

Holds the actual failing data for a BIST data check failure.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_MEM_INIT_START

Command to initiate memory initialization BIST for the memory interface specified using the instance ID. Memory initialization programming allows a selectable range of memory to be initialized with a programmable data value. This command MUST be followed by BIST_MEM_INIT_STATUS to get the results of the BIST memory initialization operation and resume normal operation of the memory controller.

[Inputs] N/A

CMD_PARAM_0 [5:0]: BIST_ADDR_SPACE [5:0]

Used in BIST data checking to define the address space in bytes from 0 to 2addr_space that the BIST logic checks. As an example, if the BIST_ADDR_SPACE parameter was programmed to 0x1c, then the BIST logic would check 228 bytes = 256 MBytes. Note: A BIST test must cover a minimum of 2 bursts. Therefore, you must program this parameter to a value such that the start address and end address of the BIST test encompass a minimum of 2 bursts. Only used if BIST_FULL_MEM is ‘b0.

CMD_PARAM_0 [6:6]: BIST_FULL_MEM

Defines whether to perform BIST on full memory or on the specified address range.

‘b0 – BIST performed on address range specified using BIST_START_ADDR and BIST_ADDR_SPACE

‘b1 – BIST performed on full memory address range

CMD_PARAM_1 [31:0]: BIST_START_ADDR [31:0]

CMD_PARAM_2 [5:0]: BIST_START_ADDR [37:32]

Used in BIST data checking and memory initialization programming to define the starting address for BIST checking in bytes. Only used if BIST_FULL_MEM is ‘b0.

CMD_PARAM_3: BIST_DATA_PATTERN

Specifies the data pattern to use for the memory initialization.

‘b00 – Initialize memory to all zeros.

‘b10 – Use data pattern specified using the values set using commands BIST_SET_DATA_PATTERN_UPPER and BIST_SET_DATA_PATTERN_LOWER before issuing BIST_MEM_INITIAL_START command.

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: BIST_INITIATED

‘b1 – BIST memory initialization initiated successfully

‘b0 – BIST memory initialization initiation failed

[Command-Specific Errors]

‘b00 – No errors

‘b01 – A previous command’s saved state not restored. For example, BIST_STANDARD_MODE_START should be followed by BIST_RESULTS_STATUS command to restored saved state and resume normal memory controller operation.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_MEM_INIT_STATUS

Command to get BIST memory initialization status for the previously initiated BIST operation for memory interface specified using the instance ID

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT [0:0]: BIST_STATUS

Holds the status of the BIST operation.

’b0 = BIST operation still in progress if previously initiated.

’b1 = BIST operation has been completed.

[Command-Specific Errors]

‘b00 – No errors

‘b01 – Could not restore saved state. BIST_MEM_INIT_START command MUST be immediately followed by BIST_MEM_INIT_STATUS to get the results of the BIST operation, restore saved state, and resume normal operation of the memory controller. The populated results, if any, may be invalid.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_SET_DATA_PATTERN_UPPER

CMD_PARAM_3 [31:0]: BIST_DATA_PATTERN [287:256]

CMD_PARAM_2 [31:0]: BIST_DATA_PATTERN [255:224]

CMD_PARAM_1 [31:0]: BIST_DATA_PATTERN [223:192]

CMD_PARAM_0 [31:0]: BIST_DATA_PATTERN [191:160]

Defines the data pattern bits [287:160] to be used. Only data corresponding to active portion of core word is used while the inactive portion is ignored.

[Outputs] N/A

[Command-Specific Errors]

‘b00 – No errors

‘b01 – Cannot set upper data pattern for slim interface.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = BIST_SET_DATA_PATTERN_LOWER

CMD_PARAM_4 [31:0]: BIST_DATA_PATTERN [159:128]

CMD_PARAM_3 [31:0]: BIST_DATA_PATTERN [127:96]

CMD_PARAM_2 [31:0]: BIST_DATA_PATTERN [95:64]

CMD_PARAM_1 [31:0]: BIST_DATA_PATTERN [63:32]

CMD_PARAM_0 [31:0]: BIST_DATA_PATTERN [31:0]

Defines the data pattern bits [223:0] to be used. Only data corresponding to active portion of the core word is used while inactive portion is ignored.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = LP_MODE_ENTER

Command to cause the Interface to enter a low power state. Note that other interface operations, including recalibration and mode register reads and writes, can cause automatic exits from some low-power states.

[Inputs]

CMD_PARAM_0[3:0]:

The low power state the interface enters

‘b0001 – Active Power Down (All Protocols)

‘b0010 – Active Power Down with Memory Clock Gating (LPDDR4/LPDDR5 Only)

‘b0011 – Pre-Charge Power Down (All Protocols)

‘b0100 – Pre-Charge Power Down with Memory Clock Gating (LPDDR4/LPDDR5 Only)

‘b0101 – Self-Refresh Short (DDR4/DDR5 and LPDDR4 Only)

‘b0110 – Self-Refresh Short with Memory Clock Gating (DDR4/DDR5 Only)

‘b1000 – Self-Refresh Long (DDR4/DDR5 Only)

‘b1001 – Self-Refresh Long with Memory Clock Gating (DDR4/DDR5 Only)

‘b1010 – Self-Refresh Long with Memory Clock and Controller Clock Gating (DDR4/DDR5 Only)

‘b1011 – Self-Refresh Power Down Short (LPDDR4/LPDDR5 Only)

‘b1100 – Self-Refresh Power Down Short with Memory Clock Gating (LPDDR4/LPDDR5 Only)

‘b1101 – Self-Refresh Power Down Long (LPDDR4/LPDDR5 Only)

‘b1110 – Self-Refresh Power Down Long with Memory Clock Gating (LPDDR4/LPDDR5 Only)

‘b1111 – Self-Refresh Power Down Long with Memory and Controller Clock Gating (LPDDR4/LPDDR5 Only)

[Outputs] N/A

[Error Codes]

‘b000 – No errors

‘b001 – The Selected Low Power State is Not Available for the Current Protocol

‘b010 – The Selected Low Power State is invalid/Does not Exist.

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = LP_MODE_EXIT

Command to exit any low power state.

[Inputs] N/A

[Outputs] N/A

[Error Codes]

‘b000 – No errors

CMD_REQ [31:29]: CMD_TARGET_IP_TYPE = <TARGET_IP_TYPE>

CMD_REQ [28:24]: CMD_TARGET_IP_INSTANCE_ID = <TARGET_IP_INSTANCE_ID>

CMD_REQ [23:16]: CMD_TYPE = CMD_TRIG_CONTROLLER_OP

CMD_REQ [15:0]: CMD_OPCODE = LP_MODE_STATUS

Command to get the Current Low Power State of the Interface.

[Inputs] N/A

[Outputs]

CMD_RESPONSE_DATA_SHORT[0:0]:

Valid Bit. The Data in CMD_RESPONSE_DATA_0[5:0] is only valid if this bit is ‘b1.

‘b0 – Invalid, the Interface is currently transitioning into or out of a low power state

‘b1 – Valid.

CMD_RESPONSE_DATA_0[5:0]: Current Interface Low Power State

‘b000000 - Idle

‘b000001 – Active Power Down

‘b000010 – Active Power Down with Memory Clock Gating

‘b000011 – Pre-Charge Power Down

‘b000100 – Pre-Charge Power Down with Memory Clock Gating

‘b000101 – Self-Refresh Short

‘b000110 – Self-Refresh Short with Memory Clock Gating

‘b001000 – Self-Refresh Long

‘b001001 – Self-Refresh Long with Memory Clock Gating

‘b001010 – Self-Refresh Long with Memory Clock and Controller Clock Gating

‘b001011 – Self-Refresh Power Down Short

‘b001100 – Self-Refresh Power Down Short with Memory Clock Gating

‘b001101 – Self-Refresh Power Down

‘b001110 – Self-Refresh Power Down Long with Memory Clock Gating

‘b001111 – Self-Refresh Power Down Long with Memory and Controller Clock Gating

[Error Codes]

‘b000 – No errors
Level Two Title