External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

8.2.2.2. PLL

When using PLL for external memory interfaces, you must consider the following guidelines.

For the clock source, use the clock input pin specifically dedicated to the PLL that you want to use with your external memory interface. The input and output pins are only fully compensated when you use the dedicated PLL clock input pin. Agilex™ 5 devices support only differential I/O standard on dedicated PLL clock input pin for EMIF IP.

Intel recommends using the fastest possible PLL reference clock frequency available in the drop-down list in the EMIF IP Platform Designer, because doing so provides the best jitter performance.

For specific pin connection requirements, refer to Specific Pin Connection Requirements.