External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment

In Agilex™ 5 external memory interfaces, a global clock network clocks registers inside the FPGA core, and the PHY clock network clocks registers inside the FPGA periphery. Clock phase alignment circuitry employs negative feedback to dynamically adjust the phase of the core clock signal to match the phase of the PHY clock signal.

The clock phase alignment feature effectively eliminates the clock skew effect in all transfers between the core and the periphery, facilitating timing closure. All Agilex™ 5 external memory interfaces employ clock phase alignment circuitry.

Figure 9. Clock Phase Alignment Illustration

Clock Phase Alignment Illustration

Figure 10. Effect of Clock Phase Alignment

Clock Phase Alignment Timing Diagrams