External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

3.4.1. Hard Memory Controller

The Agilex™ 5 hard memory controller is designed for high speed, high performance, high flexibility, and area efficiency. The Agilex™ 5 hard memory controller supports the DDR4 and LPDDR4 memory standards.

The hard memory controller implements efficient pipelining techniques and advanced dynamic command and data reordering algorithms to improve bandwidth usage and reduce latency, providing a high-performance solution.

The hard memory controller consists of the following logic blocks:

  • Core and PHY interfaces
  • Main control path
  • Data buffer controller
  • Read and write data buffers

The controller user interface uses the AXI4 protocol. The controller communicates to the PHY using the DDR PHY Interface (DFI).