External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

10.1.1. Timing Analysis

Timing analysis of Agilex™ 5 EMIF IP is somewhat simpler than that of some earlier device families, because Agilex™ 5 devices have more hardened blocks and fewer soft logic registers to be analyzed, because most are user logic registers.

Your Agilex™ 5 EMIF IP includes a Synopsys Design Constraints File (.sdc) which contains timing constraints specific to your IP. The .sdc file also contains Tool Command Language (.tcl) scripts which perform various timing analyses specific to memory interfaces.