External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology

A single channel with 1 rank and x16 memory devices, this interface covers data bytes (DQ/DQS), address signals, command signals (BA, BG, RAS, CAS, WE, ACT, PAR), control signals (CKE, CS, ODT) and clocks (CLK).

The following figure illustrates the stripline routing for inner pins, for the signal connection topology for 1 rank x 16 memory down configuration.

Figure 26. Stripline Routing for DDR4 1 Rank x 16 Discrete Topology

The following figure illustrates the microstrip routing for edge pins, per byte.

Figure 27. Microstrip Routing for DDR4 1 Rank x 16 Discrete Topology

The following table shows the stripline routing guideline for inner pins.

Table 107.  Stripline Routing Guideline for GPIO Inner Pins

The following table shows the microstrip routing guideline for edge pins,per byte.

Table 108.  Microstrip Routing Guideline for GPIO Edge Pins