External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Agilex™ 5 FPGA EMIF IP - DDR5 Support 8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 10. Agilex™ 5 FPGA EMIF IP – Timing Closure 11. Agilex™ 5 FPGA EMIF IP – Controller Optimization 12. Agilex™ 5 FPGA EMIF IP – Debugging 13. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Lockstep Configuration 3.2.3.2. Pin Placement 3.2.3.3. HSIO Sub-Bank Usage
3.3. Agilex™ 5 EMIF Sequencer x
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions x
3.3.1.1. Mailbox Supported Commands 3.3.1.2. Mailbox Command Definitions
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. Agilex 5 EMIF IP Interfaces for DDR4 4.2. Agilex 5 EMIF IP Interfaces for DDR5 4.3. Agilex 5 EMIF IP Interfaces for LPDDR4 4.4. Agilex 5 EMIF IP Interfaces for LPDDR5 4.5. Agilex 5 EMIF IP Interfaces for the EMIF Calibration Component
4.1. Agilex 5 EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF IP 4.1.2. core_init_n for EMIF IP 4.1.3. usr_async_clk for EMIF IP 4.1.4. usr_clk for EMIF IP 4.1.5. usr_rst_n for EMIF IP 4.1.6. s0_axi4 for EMIF IP 4.1.7. mem for EMIF IP 4.1.8. oct for EMIF IP
4.2. Agilex 5 EMIF IP Interfaces for DDR5 x
4.2.1. ref_clk for EMIF IP 4.2.2. core_init_n for EMIF IP 4.2.3. usr_async_clk for EMIF IP 4.2.4. usr_clk for EMIF IP 4.2.5. usr_rst_n for EMIF IP 4.2.6. s0_axi4 for EMIF IP 4.2.7. mem for EMIF IP 4.2.8. i3c for EMIF IP 4.2.9. mem_lbd for EMIF IP 4.2.10. mem_lbs for EMIF IP 4.2.11. oct for EMIF IP
4.3. Agilex 5 EMIF IP Interfaces for LPDDR4 x
4.3.1. ref_clk for EMIF IP 4.3.2. core_init_n for EMIF IP 4.3.3. usr_async_clk for EMIF IP 4.3.4. usr_clk for EMIF IP 4.3.5. usr_rst_n for EMIF IP 4.3.6. s0_axi4 for EMIF IP 4.3.7. mem for EMIF IP 4.3.8. oct for EMIF IP
4.4. Agilex 5 EMIF IP Interfaces for LPDDR5 x
4.4.1. ref_clk for EMIF IP 4.4.2. core_init_n for EMIF IP 4.4.3. usr_async_clk for EMIF IP 4.4.4. usr_clk for EMIF IP 4.4.5. usr_rst_n for EMIF IP 4.4.6. s0_axi4 for EMIF IP 4.4.7. mem for EMIF IP 4.4.8. oct for EMIF IP
4.5. Agilex 5 EMIF IP Interfaces for the EMIF Calibration Component x
4.5.1. s0_axi4lite_clk for EMIF IP Calibration Component 4.5.2. s0_axi4lite_rst_n for EMIF IP Calibration Component 4.5.3. s0_axil for EMIF IP Calibration Component
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR4 6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.3. Agilex™ 5 EMIF Pin Swapping Guidelines 6.4. DDR4 Layout Design Guidelines
6.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR4 x
6.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for DDR4 6.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions 6.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.1. Agilex™ 5 FPGA EMIF IP Resources 6.2.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 6.2.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP
6.2.1. Agilex™ 5 FPGA EMIF IP Resources x
6.2.1.1. OCT 6.2.1.2. PLL
6.2.2. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
6.2.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.2.2.1. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.2.1.1. Agilex™ 5 FPGA EMIF IP Interface Pins 6.2.2.1.2. Estimating Pin Requirements 6.2.2.1.3. Maximum Number of Interfaces
6.2.3. Pin Placements for Agilex™ 5 FPGA DDR4 EMIF IP x
6.2.3.1. Address and Command Pin Placement for DDR4 6.2.3.2. DDR4 Data Width Mapping 6.2.3.3. General Guidelines 6.2.3.4. x4 DIMM Implementation 6.2.3.5. Specific Pin Connection Requirements 6.2.3.6. Command and Address Signals 6.2.3.7. Clock Signals 6.2.3.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.3.1. DDR4 Byte Lane Swapping 6.3.2. DDR4 Address and Command and CLK Lane 6.3.3. DDR4 Interface x8 Data Lane 6.3.4. DDR4 Interface x4 Data Lane
6.4. DDR4 Layout Design Guidelines x
6.4.1. DDR4 PCB Stackup and Design Considerations 6.4.2. DDR4 General Design Considerations 6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies
6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies x
6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology 6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations 6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations 6.4.3.6. DDR4 Simulation Strategy
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support x
7.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR5 7.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
7.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR5 x
7.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for DDR5 7.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions 7.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
7.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 7.2.2. Agilex™ 5 FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 7.2.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP 7.2.5. Agilex™ 5 EMIF Pin Swapping Guidelines
7.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. DIMM Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Agilex™ 5 FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
7.2.3.1. General Guidelines - DDR5 7.2.3.2. x4 DIMM Implementation 7.2.3.3. Specific Pin Connection Requirements 7.2.3.4. Command and Address Signals 7.2.3.5. Clock Signals 7.2.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.2.4. Pin Placements for Agilex™ 5 FPGA DDR5 EMIF IP x
7.2.4.1. Address and Command Pin Placement for DDR5 7.2.4.2. DDR5 Data Width Mapping
7.2.5. Agilex™ 5 EMIF Pin Swapping Guidelines x
7.2.5.1. DDR5 Byte Lane Swapping 7.2.5.2. DDR5 Address and Command and CLK Lane 7.2.5.3. DDR5 Interface x8 Data Lane 7.2.5.4. DDR5 Interface x4 Data Lane 7.2.5.5. Pin Swizzling
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
8.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR4 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR4 Layout Design Guidelines
8.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR4 x
8.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for LPDDR4 8.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR4) Parameter Descriptions 8.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR4 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals 8.2.3.5. Address and Command Pin Placement for LPDDR4 8.2.3.6. LPDDR4 Data Width Mapping 8.2.3.7. Pin Swapping Guidelines
8.3. LPDDR4 Layout Design Guidelines x
8.3.1. LPDDR4 PCB Stackup and Design Considerations 8.3.2. LPDDR4 General Design Considerations 8.3.3. LPDDR4 Interface Design Guidelines
8.3.3. LPDDR4 Interface Design Guidelines x
8.3.3.1. LPDDR4 Discrete Component/Memory Down Topology (up to 32 bits interface) 8.3.3.2. LPDDR4 Simulation Strategy
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
9.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR5 9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 9.3. LPDDR5 Layout Design Guidelines
9.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for LPDDR5 x
9.1.1. Agilex 5 FPGA External Memory Interfaces (EMIF) IP Parameter Descriptions for LPDDR5 9.1.2. Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions 9.1.3. Agilex 5 FPGA EMIF Calibration IP Parameter Descriptions
9.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 9.2.2. Agilex™ 5 FPGA EMIF IP Resources 9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP
9.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
9.2.1.1. Estimating Pin Requirements 9.2.1.2. LPDDR5 Component Options 9.2.1.3. Maximum Number of Interfaces
9.2.2. Agilex™ 5 FPGA EMIF IP Resources x
9.2.2.1. OCT 9.2.2.2. PLL
9.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
9.2.3.1. General Guidelines - LPDDR5 9.2.3.2. Specific Pin Connection Requirements 9.2.3.3. Command and Address Signals 9.2.3.4. Clock Signals
9.2.4. Pin Placements for Agilex™ 5 FPGA LPDDR5 EMIF IP x
9.2.4.1. Address and Command Pin Placement for LPDDR5 9.2.4.2. LPDDR5 Data Width Mapping 9.2.4.3. LPDDR5 Byte Lane Swapping
9.3. LPDDR5 Layout Design Guidelines x
9.3.1. LPDDR5 PCB Stackup and Design Considerations 9.3.2. LPDDR5 General Design Considerations 9.3.3. LPDDR5 Interface Design Guidelines
9.3.3. LPDDR5 Interface Design Guidelines x
9.3.3.1. LPDDR5 Discrete Component/Memory Down Topology (Single Rank or Dual-Rank) 9.3.3.2. Example of an LPDDR5 Layout on an Intel FPGA Platform Board 9.3.3.3. LPDDR5 Simulation Strategy
10. Agilex™ 5 FPGA EMIF IP – Timing Closure x
10.1. Timing Closure 10.2. Optimizing Timing
10.1. Timing Closure x
10.1.1. Timing Analysis
10.1.1. Timing Analysis x
10.1.1.1. PHY or Core
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
11.1. Interface Standard 11.2. Bank Management Efficiency 11.3. Data Transfer 11.4. Improving Controller Efficiency
11.4. Improving Controller Efficiency x
11.4.1. Frequency of Operation 11.4.2. Series of Reads or Writes
12. Agilex™ 5 FPGA EMIF IP – Debugging x
12.1. Interface Configuration Performance Issues 12.2. Functional Issue Evaluation 12.3. Timing Issue Characteristics 12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 12.5. Debugging with the External Memory Interface Debug Toolkit 12.6. Generating Traffic with the Test Engine IP 12.7. Guidelines for Developing HDL for Traffic Generator 12.8. Guidelines for Traffic Generator Status Check 12.9. Hardware Debugging Guidelines 12.10. Create a Simplified Design that Demonstrates the Same Issue 12.11. Measure Power Distribution Network 12.12. Measure Signal Integrity and Setup and Hold Margin 12.13. Vary Voltage 12.14. Operate at a Lower Speed 12.15. Determine Whether the Issue Exists in Previous Versions of Software 12.16. Determine Whether the Issue Exists in the Current Version of Software 12.17. Try A Different PCB 12.18. Try Other Configurations 12.19. Debugging Checklist 12.20. Categorizing Hardware Issues 12.21. Signal Integrity Issues 12.22. Characteristics of Signal Integrity Issues 12.23. Evaluating Signal Integrity Issues 12.24. Skew 12.25. Crosstalk 12.26. Power System 12.27. Clock Signals 12.28. Address and Command Signals 12.29. Read Data Valid Window and Eye Diagram 12.30. Write Data Valid Window and Eye Diagram 12.31. Hardware and Calibration Issues 12.32. Memory Timing Parameter Evaluation 12.33. Verify that the Board Has the Correct Memory Component or DIMM Installed
12.1. Interface Configuration Performance Issues x
12.1.1. Interface Configuration Bottleneck and Efficiency Issues
12.2. Functional Issue Evaluation x
12.2.1. Altera IP Memory Model 12.2.2. Vendor Memory Model 12.2.3. Transcript Window Messages
12.3. Timing Issue Characteristics x
12.3.1. Evaluating FPGA Timing Issues 12.3.2. Evaluating External Memory Interface Timing Issues
12.5. Debugging with the External Memory Interface Debug Toolkit x
12.5.1. Prerequisites for Using the EMIF Debug Toolkit 12.5.2. Configuring a Design to Use the Debug Toolkit 12.5.3. Launching the EMIF Debug Toolkit 12.5.4. Using the EMIF Debug Toolkit
12.5.2. Configuring a Design to Use the Debug Toolkit x
12.5.2.1. Generating a Design Example with the Debug Toolkit
12.5.4. Using the EMIF Debug Toolkit x
12.5.4.1. Running Re-Calibration 12.5.4.2. Running the Test Engine
12.8. Guidelines for Traffic Generator Status Check x
12.8.1. Status Check Using the Signal Tap Logic Analyzer 12.8.2. Exporting the Status Interface to the Top-Level Design
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

3.2.3.2. Pin Placement

Table 12.  DDR4 Pin Placement
Lane Number Pin Index x32+ECC * x 32 x16 + ECC * x16
BL7 95 MEM_DQ[39]*      
94 MEM_DQ[38] *      
93 MEM_DQ[37] *      
92 MEM_DQ[36] *      
91        
90 MEM_DM_N[4]      
89 MEM_DQS_C[4]      
88 MEM_DQS_T[4]      
87 MEM_DQ[35] *      
86 MEM_DQ[34] *      
85 MEM_DQ[33] *      
84 MEM_DQ[32] *      
BL6 83 MEM_DQ[31] MEM_DQ[31]    
82 MEM_DQ[30] MEM_DQ[30]    
81 MEM_DQ[29] MEM_DQ[29]    
80 MEM_DQ[28] MEM_DQ[28]    
79        
78 MEM_DM_N[3] MEM_DM_N[3]    
77 MEM_DQS_C[3] MEM_DQS_C[3]    
76 MEM_DQS_T[3] MEM_DQS_T[3]    
75 MEM_DQ[27] MEM_DQ[27]    
74 MEM_DQ[26] MEM_DQ[26]    
73 MEM_DQ[25] MEM_DQ[25]    
72 MEM_DQ[24] MEM_DQ[24]    
BL5 71 MEM_DQ[23] MEM_DQ[23] MEM_DQ[23] *  
70 MEM_DQ[22] MEM_DQ[22] MEM_DQ[22] *  
69 MEM_DQ[21] MEM_DQ[21] MEM_DQ[21] *  
68 MEM_DQ[20] MEM_DQ[20] MEM_DQ[20] *  
67        
66 MEM_DM_N[2] MEM_DM_N[2] MEM_DM_N[2]  
65 MEM_DQS_C[2] MEM_DQS_C[2] MEM_DQS_C[2]  
64 MEM_DQS_T[2] MEM_DQS_T[2] MEM_DQS_T[2]  
63 MEM_DQ[19] MEM_DQ[19] MEM_DQ[19] *  
62 MEM_DQ[18] MEM_DQ[18] MEM_DQ[18] *  
61 MEM_DQ[17] MEM_DQ[17] MEM_DQ[17] *  
60 MEM_DQ[16] MEM_DQ[16] MEM_DQ[16] *  
BL4 59 MEM_DQ[15] MEM_DQ[15] MEM_DQ[15] MEM_DQ[15]
58 MEM_DQ[14] MEM_DQ[14] MEM_DQ[14] MEM_DQ[14]
57 MEM_DQ[13] MEM_DQ[13] MEM_DQ[13] MEM_DQ[13]
56 MEM_DQ[12] MEM_DQ[12] MEM_DQ[12] MEM_DQ[12]
55        
54 MEM_DM_N[1] MEM_DM_N[1] MEM_DM_N[1] MEM_DM_N[1]
53 MEM_DQS_C[1] MEM_DQS_C[1] MEM_DQS_C[1] MEM_DQS_C[1]
52 MEM_DQS_T[1] MEM_DQS_T[1] MEM_DQS_T[1] MEM_DQS_T[1]
51 MEM_DQ[11] MEM_DQ[11] MEM_DQ[11] MEM_DQ[11]
50 MEM_DQ[10] MEM_DQ[10] MEM_DQ[10] MEM_DQ[10]
49 MEM_DQ[9] MEM_DQ[9] MEM_DQ[9] MEM_DQ[9]
48 MEM_DQ[8] MEM_DQ[8] MEM_DQ[8] MEM_DQ[8]
BL3 47 MEM_BG[0] MEM_BG[0] MEM_BG[0] MEM_BG[0]
46 MEM_BA[1] MEM_BA[1] MEM_BA[1] MEM_BA[1]
45 MEM_BA[0] MEM_BA[0] MEM_BA[0] MEM_BA[0]
44 MEM_ALERT_N[0] MEM_ALERT_N[0] MEM_ALERT_N[0] MEM_ALERT_N[0]
43 MEM_A[16] MEM_A[16] MEM_A[16] MEM_A[16]
42 MEM_A[15] MEM_A[15] MEM_A[15] MEM_A[15]
41 MEM_A[14] MEM_A[14] MEM_A[14] MEM_A[14]
40 MEM_A[13] MEM_A[13] MEM_A[13] MEM_A[13]
39 MEM_A[12] MEM_A[12] MEM_A[12] MEM_A[12]
38 RZQ Site RZQ Site RZQ Site RZQ Site
37 Differential "N-Side" Reference Clock Input Site Differential "N-Side" Reference Clock Input Site Differential "N-Side" Reference Clock Input Site Differential "N-Side" Reference Clock Input Site
36 Differential "P-Side" Reference Clock Input Site Differential "P-Side" Reference Clock Input Site Differential "P-Side" Reference Clock Input Site Differential "P-Side" Reference Clock Input Site
BL2 35 MEM_A[11] MEM_A[11] MEM_A[11] MEM_A[11]
34 MEM_A[10] MEM_A[10] MEM_A[10] MEM_A[10]
33 MEM_A[9] MEM_A[9] MEM_A[9] MEM_A[9]
32 MEM_A[8] MEM_A[8] MEM_A[8] MEM_A[8]
31 MEM_A[7] MEM_A[7] MEM_A[7] MEM_A[7]
30 MEM_A[6] MEM_A[6] MEM_A[6] MEM_A[6]
29 MEM_A[5] MEM_A[5] MEM_A[5] MEM_A[5]
28 MEM_A[4] MEM_A[4] MEM_A[4] MEM_A[4]
27 MEM_A[3] MEM_A[3] MEM_A[3] MEM_A[3]
26 MEM_A[2] MEM_A[2] MEM_A[2] MEM_A[2]
25 MEM_A[1] MEM_A[1] MEM_A[1] MEM_A[1]
24 MEM_A[0] MEM_A[0] MEM_A[0] MEM_A[0]
BL1 23 MEM_PAR[0] MEM_PAR[0] MEM_PAR[0] MEM_PAR[0]
22 MEM_CS_N[1] MEM_CS_N[1] MEM_CS_N[1] MEM_CS_N[1]
21 MEM_CK_C[0] MEM_CK_C[0] MEM_CK_C[0] MEM_CK_C[0]
20 MEM_CK_T[0] MEM_CK_T[0] MEM_CK_T[0] MEM_CK_T[0]
19 MEM_CKE[1] MEM_CKE[1] MEM_CKE[1] MEM_CKE[1]
18 MEM_CKE[0] MEM_CKE[0] MEM_CKE[0] MEM_CKE[0]
17 MEM_ODT[1] MEM_ODT[1] MEM_ODT[1] MEM_ODT[1]
16 MEM_ODT[0] MEM_ODT[0] MEM_ODT[0] MEM_ODT[0]
15 MEM_ACT_N[0] MEM_ACT_N[0] MEM_ACT_N[0] MEM_ACT_N[0]
14 MEN_CS_N[0] MEN_CS_N[0] MEN_CS_N[0] MEN_CS_N[0]
13 MEM_RESET_N[0] MEM_RESET_N[0] MEM_RESET_N[0] MEM_RESET_N[0]
12 MEM_BG[1] MEM_BG[1] MEM_BG[1] MEM_BG[1]
BL0 11 MEM_DQ[7] MEM_DQ[7] MEM_DQ[7] MEM_DQ[7]
10 MEM_DQ[6] MEM_DQ[6] MEM_DQ[6] MEM_DQ[6]
9 MEM_DQ[5] MEM_DQ[5] MEM_DQ[5] MEM_DQ[5]
8 MEM_DQ[4] MEM_DQ[4] MEM_DQ[4] MEM_DQ[4]
7        
6 MEM_DM_N[0] MEM_DM_N[0] MEM_DM_N[0] MEM_DM_N[0]
5 MEM_DQS_C[0] MEM_DQS_C[0] MEM_DQS_C[0] MEM_DQS_C[0]
4 MEM_DQS_T[0] MEM_DQS_T[0] MEM_DQS_T[0] MEM_DQS_T[0]
3 MEM_DQ[3] MEM_DQ[3] MEM_DQ[3] MEM_DQ[3]
2 MEM_DQ[2] MEM_DQ[2] MEM_DQ[2] MEM_DQ[2]
1 MEM_DQ[1] MEM_DQ[1] MEM_DQ[1] MEM_DQ[1]
0 MEM_DQ[0] MEM_DQ[0] MEM_DQ[0] MEM_DQ[0]
Note: The presence of an asterisk (*) in the above table indicates an ECC byte location.
Table 13.  DDR5 Pin Placement
Lane Number Pin Index x32+ECC * x 32 2ch x16 x16 + ECC * x16
BL7 95     MEM_1_MEM_DQ[15]    
94     MEM_1_MEM_DQ[14]    
93     MEM_1_MEM_DQ[13]    
92     MEM_1_MEM_DQ[12]    
91          
90     MEM_1_MEM_DM_N[1]    
89     MEM_1_MEM_DQS_C[1]    
88     MEM_1_MEM_DQS_T[1]    
87     MEM_1_MEM_DQ[11]    
86     MEM_1_MEM_DQ[10]    
85     MEM_1_MEM_DQ[9]    
84     MEM_1_MEM_DQ[8]    
BL6 83 MEM_DQ[39]*   MEM_1_MEM_DQ[7]    
82 MEM_DQ[38]*   MEM_1_MEM_DQ[6]    
81 MEM_DQ[37]*   MEM_1_MEM_DQ[5]    
80 MEM_DQ[36]*   MEM_1_MEM_DQ[4]    
79          
78 MEM_DM_N[4]   MEM_1_MEM_DM_N[0]    
77 MEM_DQS_C[4]   MEM_1_MEM_DQS_C[0]    
76 MEM_DQS_T[4]   MEM_1_MEM_DQS_T[0]    
75 MEM_DQ[35]*   MEM_1_MEM_DQ[3]    
74 MEM_DQ[34]*   MEM_1_MEM_DQ[2]    
73 MEM_DQ[33]*   MEM_1_MEM_DQ[1]    
72 MEM_DQ[32]*   MEM_1_MEM_DQ[0]    
BL5 71 MEM_DQ[31] MEM_DQ[31] MEM_1_CK_C[1]    
70 MEM_DQ[30] MEM_DQ[30] MEM_1_CK_T[1]    
69 MEM_DQ[29] MEM_DQ[29] MEM_1_MEM_CS_N[0]    
68 MEM_DQ[28] MEM_DQ[28] MEM_1_MEM_CS_N[1]    
67     MEM_1_CK_C[0]    
66 MEM_DM_N[3] MEM_DM_N[3] MEM_1_CK_T[0]    
65 MEM_DQS_C[3] MEM_DQS_C[3] MEM_1_MEM_CA[12]    
64 MEM_DQS_T[3] MEM_DQS_T[3] MEM_1_MEM_CA[11]    
63 MEM_DQ[27] MEM_DQ[27] MEM_1_RESET_N    
62 MEM_DQ[26] MEM_DQ[26] OCT_1_OCT_RZQIN    
61 MEM_DQ[25] MEM_DQ[25] MEM_1_ALERT_N    
60 MEM_DQ[24] MEM_DQ[24] MEM_1_MEM_CA[10]    
BL4 59 MEM_DQ[23] MEM_DQ[23]

Differential "NSide" Reference Clock Input Site

 MEM_DQ[23]*  
58 MEM_DQ[22] MEM_DQ[22]

Differential "PSide" Reference Clock Input Site

 MEM_DQ[22]*  
57 MEM_DQ[21] MEM_DQ[21] MEM_1_MEM_CA[9] MEM_DQ[21]*  
56 MEM_DQ[20] MEM_DQ[20] MEM_1_MEM_CA[8] MEM_DQ[20]*  
55     MEM_1_MEM_CA[7]    
54 MEM_DM_N[2] MEM_DM_N[2] MEM_1_MEM_CA[6] MEM_DM_N[2]  
53 MEM_DQS_C[2] MEM_DQS_C[2] MEM_1_MEM_CA[5] MEM_DQS_C[2]  
52 MEM_DQS_T[2] MEM_DQS_T[2] MEM_1_MEM_CA[4] MEM_DQS_T[2]  
51 MEM_DQ[19] MEM_DQ[19] MEM_1_MEM_CA[3] MEM_DQ[19]*  
50 MEM_DQ[18] MEM_DQ[18] MEM_1_MEM_CA[2] MEM_DQ[18]*  
49 MEM_DQ[17] MEM_DQ[17] MEM_1_MEM_CA[1] MEM_DQ[17]*  
48 MEM_DQ[16] MEM_DQ[16] MEM_1_MEM_CA[0] MEM_DQ[16]*  
BL3 47 MEM_CK_C[1] MEM_CK_C[1] MEM_0_CK_C[1] MEM_CK_C[1] MEM_CK_C[1]
46 MEM_CK_T[1] MEM_CK_T[1] MEM_0_CK_T[1] MEM_CK_T[1] MEM_CK_T[1]
45 MEM_CS_N[0] MEM_CS_N[0] MEM_0_MEM_CS_N[0] MEM_CS_N[0] MEM_CS_N[0]
44 MEM_CS_N[1] MEM_CS_N[1] MEM_0_MEM_CS_N[1] MEM_CS_N[1] MEM_CS_N[1]
43 MEM_CK_C[0] MEM_CK_C[0] MEM_0_CK_C[0] MEM_CK_C[0] MEM_CK_C[0]
42 MEM_CK_T[0] MEM_CK_T[0] MEM_0_CK_T[0] MEM_CK_T[0] MEM_CK_T[0]
41 MEM_CA[12] MEM_CA[12] MEM_0_MEM_CA[12] MEM_CA[12] MEM_CA[12]
40 MEM_CA[11] MEM_CA[11] MEM_0_MEM_CA[11] MEM_CA[11] MEM_CA[11]
39 MEM_RESET_N[0] MEM_RESET_N[0] MEM_0_RESET_N MEM_RESET_N[0] MEM_RESET_N[0]
38 RZQ Site RZQ Site OCT_0_OCT_RZQIN RZQ Site RZQ Site
37 MEM_ALERT_N[0] MEM_ALERT_N[0] MEM_0_ALERT_N MEM_ALERT_N[0] MEM_ALERT_N[0]
36 MEM_CA[10] MEM_CA[10] MEM_0_MEM_CA[10] MEM_CA[10] MEM_CA[10]
BL2 35 Differential "N-Side" Reference Clock Input Site Differential "N-Side" Reference Clock Input Site

Differential "NSide" Reference Clock Input Site

 Differential "N-Side" Reference Clock Input Site Differential "N-Side" Reference Clock Input Site
34 Differential "P-Side" Reference Clock Input Site Differential "P-Side" Reference Clock Input Site

Differential "PSide" Reference Clock Input Site

 Differential "P-Side" Reference Clock Input Site Differential "P-Side" Reference Clock Input Site
33 MEM_CA[9] MEM_CA[9] MEM_0_MEM_CA[9] MEM_CA[9] MEM_CA[9]
32 MEM_CA[8] MEM_CA[8] MEM_0_MEM_CA[8] MEM_CA[8] MEM_CA[8]
31 MEM_CA[7] MEM_CA[7] MEM_0_MEM_CA[7] MEM_CA[7] MEM_CA[7]
30 MEM_CA[6] MEM_CA[6] MEM_0_MEM_CA[6] MEM_CA[6] MEM_CA[6]
29 MEM_CA[5] MEM_CA[5] MEM_0_MEM_CA[5] MEM_CA[5] MEM_CA[5]
28 MEM_CA[4] MEM_CA[4] MEM_0_MEM_CA[4] MEM_CA[4] MEM_CA[4]
27 MEM_CA[3] MEM_CA[3] MEM_0_MEM_CA[3] MEM_CA[3] MEM_CA[3]
26 MEM_CA[2] MEM_CA[2] MEM_0_MEM_CA[2] MEM_CA[2] MEM_CA[2]
25 MEM_CA[1] MEM_CA[1] MEM_0_MEM_CA[1] MEM_CA[1] MEM_CA[1]
24 MEM_CA[0] MEM_CA[0] MEM_0_MEM_CA[0] MEM_CA[0] MEM_CA[0]
BL1 23 MEM_DQ[7] MEM_DQ[7] MEM_0_MEM_DQ[7] MEM_DQ[7] MEM_DQ[7]
22 MEM_DQ[6] MEM_DQ[6] MEM_0_MEM_DQ[6] MEM_DQ[6] MEM_DQ[6]
21 MEM_DQ[5] MEM_DQ[5] MEM_0_MEM_DQ[5] MEM_DQ[5] MEM_DQ[5]
20 MEM_DQ[4] MEM_DQ[4] MEM_0_MEM_DQ[4] MEM_DQ[4] MEM_DQ[4]
19          
18 MEM_DM_N[0] MEM_DM_N[0] MEM_0_MEM_DM_N[0] MEM_DM_N[0] MEM_DM_N[0]
17 MEM_DQS_C[0] MEM_DQS_C[0] MEM_0_MEM_DQS_C[0] MEM_DQS_C[0] MEM_DQS_C[0]
16 MEM_DQS_T[0] MEM_DQS_T[0] MEM_0_MEM_DQS_T[0] MEM_DQS_T[0] MEM_DQS_T[0]
15 MEM_DQ[3] MEM_DQ[3] MEM_0_MEM_DQ[3] MEM_DQ[3] MEM_DQ[3]
14 MEM_DQ[2] MEM_DQ[2] MEM_0_MEM_DQ[2] MEM_DQ[2] MEM_DQ[2]
13 MEM_DQ[1] MEM_DQ[1] MEM_0_MEM_DQ[1] MEM_DQ[1] MEM_DQ[1]
12 MEM_DQ[0] MEM_DQ[0] MEM_0_MEM_DQ[0] MEM_DQ[0] MEM_DQ[0]
BL0 11 MEM_DQ[15] MEM_DQ[15] MEM_0_MEM_DQ[15] MEM_DQ[15] MEM_DQ[15]
10 MEM_DQ[14] MEM_DQ[14] MEM_0_MEM_DQ[14] MEM_DQ[14] MEM_DQ[14]
9 MEM_DQ[13] MEM_DQ[13] MEM_0_MEM_DQ[13] MEM_DQ[13] MEM_DQ[13]
8 MEM_DQ[12] MEM_DQ[12] MEM_0_MEM_DQ[12] MEM_DQ[12] MEM_DQ[12]
7          
6 MEM_DM_N[1] MEM_DM_N[1] MEM_0_MEM_DM_N[1] MEM_DM_N[1] MEM_DM_N[1]
5 MEM_DQS_C[1] MEM_DQS_C[1] MEM_0_MEM_DQS_C[1] MEM_DQS_C[1] MEM_DQS_C[1]
4 MEM_DQS_T[1] MEM_DQS_T[1] MEM_0_MEM_DQS_T[1] MEM_DQS_T[1] MEM_DQS_T[1]
3 MEM_DQ[11] MEM_DQ[11] MEM_0_MEM_DQ[11] MEM_DQ[11] MEM_DQ[11]
2 MEM_DQ[10] MEM_DQ[10] MEM_0_MEM_DQ[10] MEM_DQ[10] MEM_DQ[10]
1 MEM_DQ[9] MEM_DQ[9] MEM_0_MEM_DQ[9] MEM_DQ[9] MEM_DQ[9]
0 MEM_DQ[8] MEM_DQ[8] MEM_0_MEM_DQ[8] MEM_DQ[8] MEM_DQ[8]
Note: The presence of an asterisk (*) in the above table indicates an ECC byte location.
Table 14.  LPDDR4 Pin Placement
Lane Number Pin Index x32 2 Channel x16
BL7 95 MEM_DQ[31] MEM_1_MEM_DQ[15]
94 MEM_DQ[30] MEM_1_MEM_DQ[14]
93 MEM_DQ[29] MEM_1_MEM_DQ[13]
92 MEM_DQ[28] MEM_1_MEM_DQ[12]
91    
90 MEM_DMI[3] MEM_1_MEM_DMI[1]
89 MEM_DQS_C[3] MEM_1_MEM_DQS_C[1]
88 MEM_DQS_T[3] MEM_1_MEM_DQS_T[1]
87 MEM_DQ[27] MEM_1_MEM_DQ[11]
86 MEM_DQ[26] MEM_1_MEM_DQ[10]
85 MEM_DQ[25] MEM_1_MEM_DQ[9]
84 MEM_DQ[24] MEM_1_MEM_DQ[8]
BL6 83 MEM_DQ[23] MEM_1_MEM_DQ[7]
82 MEM_DQ[22] MEM_1_MEM_DQ[6]
81 MEM_DQ[21] MEM_1_MEM_DQ[5]
80 MEM_DQ[20] MEM_1_MEM_DQ[4]
79    
78 MEM_DMI[2] MEM_1_MEM_DMI[0]
77 MEM_DQS_C[2] MEM_1_MEM_DQS_C[0]
76 MEM_DQS_T[2] MEM_1_MEM_DQS_T[0]
75 MEM_DQ[19] MEM_1_MEM_DQ[3]
74 MEM_DQ[18] MEM_1_MEM_DQ[2]
73 MEM_DQ[17] MEM_1_MEM_DQ[1]
72 MEM_DQ[16] MEM_1_MEM_DQ[0]
BL5 71    
70    
69    
68    
67   MEM_1_MEM_CK_C
66   MEM_1_MEM_CK_T
65    
64    
63   MEM_1_MEM_RESET_N
62   OCT_1_OCT_RZQIN
61    
60    
BL4 59   Differential "N-side" reference clock input site
58   Differential "P-side" reference clock input site
57   MEM_1_MEM_CS[1]
56   MEM_1_MEM_CS[0]
55   MEM_1_MEM_CKE[1]
54   MEM_1_MEM_CKE[0]
53   MEM_1_MEM_CA[5]
52   MEM_1_MEM_CA[4]
51   MEM_1_MEM_CA[3]
50   MEM_1_MEM_CA[2]
49   MEM_1_MEM_CA[1]
48   MEM_1_MEM_CA[0]
BL3 47    
46    
45    
44    
43 MEM_CK_C MEM_0_MEM_CK_C
42 MEM_CK_T MEM_0_MEM_CK_T
41    
40    
39 MEM_RESET_N MEM_0_MEM_RESET_N
38 RZQ Site OCT_0_OCT_RZQIN
37    
36    
BL2 35 Differential "N-side" reference clock input site
34 Differential "P-side" reference clock input site
33 MEM_CS[1] MEM_0_MEM_CS[1]
32 MEM_CS[0] MEM_0_MEM_CS[0]
31 MEM_CKE[1] MEM_0_MEM_CKE[1]
30 MEM_CKE[0] MEM_0_MEM_CKE[0]
29 MEM_CA[5] MEM_0_MEM_CA[5]
28 MEM_CA[4] MEM_0_MEM_CA[4]
27 MEM_CA[3] MEM_0_MEM_CA[3]
26 MEM_CA[2] MEM_0_MEM_CA[2]
25 MEM_CA[1] MEM_0_MEM_CA[1]
24 MEM_CA[0] MEM_0_MEM_CA[0]
BL1 23 MEM_DQ[15] MEM_0_MEM_DQ[15]
22 MEM_DQ[14] MEM_0_MEM_DQ[14]
21 MEM_DQ[13] MEM_0_MEM_DQ[13]
20 MEM_DQ[12] MEM_0_MEM_DQ[12]
19    
18 MEM_DMI[1] MEM_0_MEM_DMI[1]
17 MEM_DQS_C[1] MEM_0_MEM_DQS_C[1]
16 MEM_DQS_T[1] MEM_0_MEM_DQS_T[1]
15 MEM_DQ[11] MEM_0_MEM_DQ[11]
14 MEM_DQ[10] MEM_0_MEM_DQ[10]
13 MEM_DQ[9] MEM_0_MEM_DQ[9]
12 MEM_DQ[8] MEM_0_MEM_DQ[8]
BL0 11 MEM_DQ[7] MEM_0_MEM_DQ[7]
10 MEM_DQ[6] MEM_0_MEM_DQ[6]
9 MEM_DQ[5] MEM_0_MEM_DQ[5]
8 MEM_DQ[4] MEM_0_MEM_DQ[4]
7    
6 MEM_DMI[0] MEM_0_MEM_DMI[0]
5 MEM_DQS_C[0] MEM_0_MEM_DQS_C[0]
4 MEM_DQS_T[0] MEM_0_MEM_DQS_T[0]
3 MEM_DQ[3] MEM_0_MEM_DQ[3]
2 MEM_DQ[2] MEM_0_MEM_DQ[2]
1 MEM_DQ[1] MEM_0_MEM_DQ[1]
0 MEM_DQ[0] MEM_0_MEM_DQ[0]
Table 15.  LPDDR5 Pin Placement
Lane Number Pin Index x32 2 Channel x16
BL7 95 MEM_DQ[31] MEM_1_MEM_DQ[15]
94 MEM_DQ[30] MEM_1_MEM_DQ[14]
93 MEM_DQ[29] MEM_1_MEM_DQ[13]
92 MEM_DQ[28] MEM_1_MEM_DQ[12]
91    
90 MEM_DMI[3] MEM_1_MEM_DMI[1]
89 MEM_RDQS_C[3] MEM_1_MEM_RDQS_C[1]
88 MEM_RDQS_T[3] MEM_1_MEM_RDQS_T[1]
87 MEM_DQ[27] MEM_1_MEM_DQ[11]
86 MEM_DQ[26] MEM_1_MEM_DQ[10]
85 MEM_DQ[25] MEM_1_MEM_DQ[9]
84 MEM_DQ[24] MEM_1_MEM_DQ[8]
BL6 83 MEM_DQ[23] MEM_1_MEM_DQ[7]
82 MEM_DQ[22] MEM_1_MEM_DQ[6]
81 MEM_DQ[21] MEM_1_MEM_DQ[5]
80 MEM_DQ[20] MEM_1_MEM_DQ[4]
79    
78 MEM_DMI[2] MEM_1_MEM_DMI[0]
77 MEM_RDQS_C[2] MEM_1_MEM_RDQS_C[0]
76 MEM_RDQS_T[2] MEM_1_MEM_RDQS_T[0]
75 MEM_DQ[19] MEM_1_MEM_DQ[3]
74 MEM_DQ[18] MEM_1_MEM_DQ[2]
73 MEM_DQ[17] MEM_1_MEM_DQ[1]
72 MEM_DQ[16] MEM_1_MEM_DQ[0]
BL5 71    
70    
69    
68   MEM_1_MEM_CS[1]
67   MEM_1_CK_C
66   MEM_1_CK_T
65   MEM_1_MEM_CS[0]
64   MEM_1_MEM_CA[6]
63   MEM_1_RESET_N
62   OCT_1_OCT_RZQIN
61    
60    
BL4 59  

Differential "NSide" Reference Clock Input Site
58  

Differential "PSide" Reference Clock Input Site
57   MEM_1_MEM_CA[5]
56   MEM_1_MEM_CA[4]
55   MEM_1_MEM_WCK_C[1]
54   MEM_1_MEM_WCK_T[1]
53   MEM_1_MEM_WCK_C[0]
52   MEM_1_MEM_WCK_T[0]
51   MEM_1_MEM_CA[3]
50   MEM_1_MEM_CA[2]
49   MEM_1_MEM_CA[1]
48   MEM_1_MEM_CA[0]
BL3 47    
46    
45    
44 MEM_CS[1] MEM_0_MEM_CS[1]
43 MEM_CK_C MEM_0_CK_C
42 MEM_CK_T MEM_0_CK_T
41 MEM_CS[0] MEM_0_MEM_CS[0]
40 MEM_CA[6] MEM_0_MEM_CA[6]
39 MEM_RESET_N MEM_0_RESET_N
38 RZQ Site OCT_0_OCT_RZQIN
37    
36    
BL2 35 Differential "N-Side" Reference Clock Input Site

Differential "NSide" Reference Clock Input Site
34 Differential "P-Side" Reference Clock Input Site

Differential "PSide" Reference Clock Input Site
33 MEM_CA[5] MEM_0_MEM_CA[5]
32 MEM_CA[4] MEM_0_MEM_CA[4]
31 MEM_WCK_C[1] MEM_0_MEM_WCK_C[1]
30 MEM_WCK_T[1] MEM_0_MEM_WCK_T[1]
29 MEM_WCK_C[0] MEM_0_MEM_WCK_C[0]
28 MEM_WCK_T[0] MEM_0_MEM_WCK_T[0]
27 MEM_CA[3] MEM_0_MEM_CA[3]
26 MEM_CA[2] MEM_0_MEM_CA[2]
25 MEM_CA[1] MEM_0_MEM_CA[1]
24 MEM_CA[0] MEM_0_MEM_CA[0]
BL1 23 MEM_DQ[15] MEM_0_MEM_DQ[15]
22 MEM_DQ[14] MEM_0_MEM_DQ[14]
21 MEM_DQ[13] MEM_0_MEM_DQ[13]
20 MEM_DQ[12] MEM_0_MEM_DQ[12]
19    
18 MEM_DMI[1] MEM_0_MEM_DMI[1]
17 MEM_RDQS_C[1] MEM_0_MEM_RDQS_C[1]
16 MEM_RDQS_T[1] MEM_0_MEM_RDQS_T[1]
15 MEM_DQ[11] MEM_0_MEM_DQ[11]
14 MEM_DQ[10] MEM_0_MEM_DQ[10]
13 MEM_DQ[9] MEM_0_MEM_DQ[9]
12 MEM_DQ[8] MEM_0_MEM_DQ[8]
BL0 11 MEM_DQ[7] MEM_0_MEM_DQ[7]
10 MEM_DQ[6] MEM_0_MEM_DQ[6]
9 MEM_DQ[5] MEM_0_MEM_DQ[5]
8 MEM_DQ[4] MEM_0_MEM_DQ[4]
7    
6 MEM_DMI[0] MEM_0_MEM_DMI[0]
5 MEM_RDQS_C[0] MEM_0_MEM_RDQS_C[0]
4 MEM_RDQS_T[0] MEM_0_MEM_RDQS_T[0]
3 MEM_DQ[3] MEM_0_MEM_DQ[3]
2 MEM_DQ[2] MEM_0_MEM_DQ[2]
1 MEM_DQ[1] MEM_0_MEM_DQ[1]
0 MEM_DQ[0] MEM_0_MEM_DQ[0]
Note:

It is important to strictly follow the pin placement for a given memory topology when assigning pin locations for your EMIF IP.

The recommended approach is to manually constrain some interface signals and allow the Quartus® Prime Fitter to place the pins. For this method of I/O placement, you must constrain the following signals:

  • PLL reference clock
  • RZQ pin
  • MEM_RESET_N

Do not change the location for the EMIF pin using a .qsf assignment or the Pin Planner if you need to swap the DQ pins within a DQS group or the DQS group to simplify board design.

Refer to the Configuring DQ Pin Swizzling topic in the External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs for more information about how to swap the DQ pin and DQS group.

For dual-rank component interfaces, you cannot have different swizzling specifications for rank 0 and rank 1.

Level Two Title