External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

6.1. Agilex 5 FPGA EMIF IP Parameter Descriptions for DDR4

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP.