External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

2.2. Agilex™ 5 EMIF IP Design Flow

Altera recommends creating an example top-level file with the desired pin outs and all interface IPs instantiated. This enables the Quartus® Prime software to validate the design and resource allocation before PCB and schematic sign off.

The following figure shows the design flow to provide the fastest out-of-the-box experience with the EMIF IP.

Figure 1. EMIF IP Design Flow