External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree

Dedicated high-speed clock networks drive I/Os in the Agilex™ 5 EMIF.

The relatively short span of the PHY clock trees results in low jitter and low duty-cycle distortion, maximizing the data valid window.

The PHY clock tree in Agilex™ 5 devices can run as fast as 1.6 GHz. All Agilex™ 5 external memory interfaces use the PHY clock trees.