GTS Transceiver PHY User Guide

ID 817660
Date 7/08/2024
Public
Document Table of Contents

8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit

To enable debugging capabilities, you must enable the Avalon® memory-mapped interface parameters in the GTS PMA/FEC Direct PHY Intel FPGA IP.

You can either activate these settings when you first instantiate the IP or modify the instances after preliminary compilation. Follow these steps to enable the settings:
  1. In the IP Components tab of the Project Navigator, right click the IP instance, and select Edit in Parameter Editor.
  2. Enable the Avalon® Memory-Mapped Interface, Direct PHY soft CSR, and Debug Endpoint on Avalon® Interface options under the Avalon® Memory-Mapped Interface tab as shown in the following figure.
    Figure 95. Parameters to Enable Transceiver Toolkit in GTS PMA/FEC Direct PHY Intel FPGA IP
  3. Connect the reference signals that the debugging logic requires, if applicable. The debug endpoint requires clock and reset signal connections. For details on how to connect these signals, refer to Configuring the GTS PMA/FEC Direct PHY FPGA IP for Hardware Testing.
  4. Click Generate HDL. After enabling parameters for all the IP instances in the design, recompile the project.