External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology

The following figure shows the reset routing scheme and setting, which you can apply to both 1 rank x 8 and 1 rank x 16 discrete topologies.

The target impedance for the reset signal is 50 ohms. The reset signal shall have at least 3 x h (where h represents trace to nearest reference plane height or distance) spacing to other nearby signals on the same layer. The end-to-end reset trace length is not limited but shall not exceed more than 5 inches to the first DRAM.

Figure 28. Reset Scheme and Setting for Memory Down (Discrete) Topology

In the above example, Altera recommends using a 1 K-ohm pull-down resistor for reset routing.

The following figure shows a VREF_CA routing scheme and setting, which you can apply to both 1 rank x 8 and 1 rank x 16 discrete topologies.

Figure 29. VREF_CA Scheme and Setting for Memory Down (Discrete) Topology

Altera recommends that you use at least a 10 mil trace width for VREF_CA routing on the PCB. The VREF_CA signal should have at least 3 x h (where h represents trace to nearest reference plane height or distance) spacing to other nearby signals on the same layer. The 1.8K ohm voltage divider circuitry shall be replaced by a 0.9K ohm resistor, pulled up to 0.6 V from the voltage regulator.