External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

4.1.5. usr_rst_n for EMIF IP

User clock domain reset interface

Table 35.  Interface: usr_rst_nInterface type: reset
Port Name Direction Description
usr_rst_n output User reset