External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

4.4.3. usr_async_clk for EMIF IP

User clock interface

Table 63.  Interface: usr_async_clkInterface type: clock
Port Name Direction Description
usr_async_clk input User clock