External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations

These skew matching guidelines apply to 1 rank x 8 and 1 rank x 16 memory down topologies.

For skew matching In the DDR4 discrete topology, board designers must follow these rules:
  • Perform length (skew) matching in time (ps) not in actual trace length, to better account for via delays when signals are routed on different layers.
  • Perform skew matching by including both package per pin skew and PCB delay (skew).
  • Skew (length) matching for the alert signal is not required.

The following table shows skew matching guidelines for DDR4 down-memory topology.

Table 109.  Skew Matching Guidelines for DDR Memory Down Topology