External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

4.2.7. mem for EMIF IP

Interface between FPGA and external memory

Table 46.  Interface: memInterface type: conduit
Port Name Direction Description
mem_ck_t output CK Clock (true)
mem_ck_c output CK Clock (complement)
mem_reset_n output Asynchronous Reset
mem_cs_n output Chip Select
mem_ca output Command/Address Bus
mem_par output Command/Address Parity
mem_dq bidir Data (read/write)
mem_dqs_t bidir Data Strobe (true)
mem_dqs_c bidir Data Strobe (complement)
mem_dm_n output Data Mask
mem_alert_n input Indicates Write CRC Error