External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 7/08/2024
Public
Document Table of Contents

8.3.3. LPDDR4 Interface Design Guidelines

This section describes PCB layout guidelines for LPDDR4 interfaces. LPDDR4 is supported by Agilex™ 5 E-Series group B devices only for memory down configurations. It supports both thin and thick PCB stackups. The maximum supported data rates vary depending on the selected topology.