Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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Document Table of Contents

22.1. UART Controller Features

The UART controller provides the following functionality and features:

  • Programmable character properties, such as number of data bits per character, optional parity bits, and number of stop bits †
  • Line break generation and detection †
  • DMA controller handshaking interface
  • Prioritized interrupt identification †
  • Programmable baud rate
  • False start bit detection †
  • Automatic flow control mode per 16750 standard †
  • Internal loopback mode support
  • 128-byte transmit and receive FIFO buffers
    • FIFO buffer status registers †
    • FIFO buffer access mode (for FIFO buffer testing) enables write of receive FIFO buffer by master and read of transmit FIFO buffer by master †
  • Shadow registers reduce software overhead and provide programmable reset †
  • Transmitter holding register empty (THRE) interrupt mode †
  • Separate thresholds for DMA request and handshake signals to maximize throughput