Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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10.3.15.1. AxUSER and AxCACHE Attributes

ARUSER[0] and AWUSER[0] Bits

The ACP distinguishes between shared and non-shared requests with the ARUSER[0] and AWUSER[0] signals. The other AxUSER signals, AxUSER[4:1] are not interpreted by the SCU and are simply forwarded to the L2 cache. They are typically set to AxUSER[4:1] = b'1111.The AxCACHE[1] attribute signals must also be set to allow L1 caches to be snooped. Sideband signals ARUSER[4:1] and AWUSER[4:1] convey the inner cache attributes.

The table below shows how the AxUSER[0] bit determines whether a request is shared or non-shared. ARUSER[0] applies to read transactions, and AWUSER[0] applies to write transactions.

Table 89.  ARUSER[0] or AWUSER[0] Sideband Signal Information

ARUSER[0] or AWUSER[0]

Sideband Signal Information

1 Shared request
0 Non-shared request

Other AxUSER bits from the ACP are not interpreted by the SCU but are forwarded to the L2 cache.

ARCACHE[4:0] and AWCACHE[4:0] Bits

The Cortex*-A9 MPU only interprets ARCACHE[1] and AWCACHE[1] from ACP requests. All other attributes are forwarded to the L2 cache. AxCACHE[1] is used in combination with AxUSER[0] to detect a coherent access. If AxCACHE[1]=0x1, (normal memory) and AxUSER[0]=0x1, then the access is considered coherent. All ACP requests with AxCACHE[1]=0x0 or AxUSER[0]=0x0 are seen as non-coherent requests.

Table 90.  ARUSER[0] or AWUSER[0] Sideband Signal Information

ARCACHE[1] or AWCACHE[1]

ARUSER[0] or AWUSER[0]

Access Type

1 1 Coherent request
0 0 Non-coherent request