Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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12.4.6.1.2. LUT Overflow Interrupt

The LUT table can be used to generate two types of interrupts.

On every single-bit error detection and correction, the address of the error is logged in the LUT. Each address logged is unique and is at the data word boundary of its RAM bank. Coherency of the address table is maintained by a valid bit.

An interrupt can be generated for each new LUT entry or only when the LUT overflows. The following table describes the interrupt result based on the INTMODE and INTONOVF values in the INTMODE register. In this table, it is assumed that interrupts have been enabled by setting the SERRINTEN bit of the Error Interrupt Enable (ERRINTEN) register.
Note: If the INTMODE bit is clear, then all errors generate an interrupt and no overflow data is logged. The INTMODE bit must be set to 1 for the LUT to log entries.
Table 116.  LUT Overflow Interrupt Configuration Options
INTMODE value INTONOVF value Result
0 X = Don't care All errors generate an interrupt. No overflow data is logged.
1 0

An interrupt is generated for each new LUT entry. Overflow detection is disabled.

Example: For a four-entry LUT, an interrupt asserts for each unique address entered in the LUT.

1 1

An interrupt is generated only when the LUT overflows.

Example: If the LUT depth is four, the occurrence of the fifth unique address causes an interrupt to assert.