Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

A.4.5. Clock Select

The boot ROM reads the clock select values to determine what frequency has been selected for the CPU clock and any interface clock during boot.

If the FPGA boot fuse is not blown, the clock select (CSEL) fuses are used to configure the main PLL and peripheral PLL. The Clock Manager samples the clock configuration on a cold and warm reset. If the hps_clk_f fuse is blown, the internal oscillator divided by 2, cb_intosc_hs_div2_clk, is used as the boot clock. If the fuse is not blown, an external oscillator is used. During boot ROM execution, the boot code configures the device clock based on the CSEL fuse settings or software code. The cb_intosc_hs_div2_clk can be considered the secure reference clock option.

Note: The terms CSEL and CLKSEL are used interchangeably in Intel® documentation to refer to clock select.

The CSEL settings are not used to configure the PLLs for the following conditions:

  • A boot from RAM (warm reset)
  • A boot from FPGA
  • The clock select is set to 0x1, indicating the clocks should not be touched.

If a bypass condition is encountered, the boot ROM checks to make sure that the boot clock has a proper source according to the security level set and if it does not, the boot ROM stalls. ROM code bypasses the PLLs at warm or cold reset under the following conditions:

  • The hps_clk_f fuse is not blown and the CSEL fuse value is 0xF. This setting is an unsecure bypass that uses the external oscillator (HPS_CLK1) as the clock source.
  • The hps_clk_f fuse is not blown and the CSEL fuses values are not 0xF, 0x1 or one of the values from 0x7 to 0xE that indicates PLL use. These are mapped to unsecure bypass using the external oscillator (HPS_CLK1) as the clock source.
  • The hps_clk fuse is set to secure clock, but the CSEL fuse value is not 0x2. This setting is considered secure bypass, using the internal oscillator as the clock source.

CSEL Fuse Encodings During Boot

The intent of the CSEL fuses is to give the user more control over the CPU clock in both non-secure and secure mode. For example, if you select CSEL=0x0 (the default) in non-secure mode, then the boot ROM configures all the clocks back to their default bypass (boot) mode and the MPU is clocked by the HPS_CLK1 (10-50 MHz). However, if you have a 10 MHz external oscillator (HPS_CLK1) and want to operate faster, then the CSEL fuses can be programmed to 0x7 for a MPU clock of 553 MHz. Similarly, if the input clock is 25 MHz and the CSEL fuses are programmed to 0x9 then the MPU clock is 800 MHz (25 * 32). If CSEL=0xA is chosen, then the same clock gives a MPU clock of 650 MHz (25 * 26). Finally, if some set of CSEL fuses have been blown, you can return to the default bypass state (CSEL=0x0) by blowing all the fuses (CSEL=0xF).

The following tables represent the clock frequencies that are available during the boot process according the boot clock that is selected. As noted previously, when the internal secure clock, cb_intosc_ls_clk, is used as the boot clock, the meaning of the CSEL fuses is slightly different.

To configure the clock speeds for second-stage boot loader execution, you need to select the clock speeds in the HPS component of Platform Designer (Standard). The tables below only apply to the boot process.

Table 321.  CSEL Encodings for hps_clk_f = 0 (Non-secure Operation)

CSEL[3:0] Fuse Value

Description

MPU Clock Value
0x0 When no fuses are blown, the boot ROM returns clocks back to their default (bypass) boot mode and the CPU is driven by the external oscillator (HPS_CLK1), which must be in the range of 10 to 50 MHz. No PLL is enabled. External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x1 All the clock codes are bypassed and the clock source is user selected. User-selected clock source
0x2 Reserved External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x3 Reserved External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x4 Reserved External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x5 Reserved External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x6 Reserved External Oscillator, HPS_CLK1 (10 to 50 MHz)
0x7 External oscillator input clock, HPS_CLK1, is in the range of 10 to 15 MHz 533 to 800 MHz
0x8 External oscillator input clock, HPS_CLK1, is in the range 15 to 20 MHz. 600 to 800 Mhz
0x9 External oscillator input clock, HPS_CLK1, is in the range 20 to 25 MHz. 640 to 800 Mhz
0xA External oscillator input clock, HPS_CLK1, is in the range 25 to 30 MHz. 666 to 800 Mhz
0xB External oscillator input clock, HPS_CLK1, is in the range 30 to 35 MHz. 685 to 800 Mhz
0xC External oscillator input clock, HPS_CLK1, is in the range 35 to 40 MHz. 700 to 800 Mhz
0xD External oscillator input clock, HPS_CLK1, is in the range 40 to 45 MHz. 711 to 800 Mhz
0xE External oscillator input clock, HPS_CLK1, is in the range 45 to 50 MHz. 720 to 800 Mhz
0xF The boot ROM returns clocks back to their default (bypass) boot mode and the CPU is driven by the external oscillator (HPS_CLK1). No PLL is enabled. External Oscillator, HPS_CLK1 (10 to 50 MHz)
Table 322.  CSEL Encodings for hps_clk_f = 1 (Secure Operation)

CSEL[3:0] Fuse Value

Description

MPU Clock Value
0x0 Bypass mode; in this mode all clocks are reset and boot mode is ensured active; cb_intosc_hs_div2_clk (cb_intosc_hs clock divided by 2) is used. cb_intosc_hs_div2_clk (60 to 200 MHz)
0x1 All the clock codes are bypassed and the clock is user selected. User-selected clock source
0x2 PLL is used with the internal oscillator (30 to 100 MHz) 120 to 800 MHz
0x3 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x4 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x5 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x6 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x7 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x8 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0x9 Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xA Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xB Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xC Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xD Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xE Reserved cb_intosc_hs_div2_clk (60 to 200 MHz)
0xF Bypass mode; reset all clocks and ensure boot mode is active; cb_intosc_hs_div2_clk is used. cb_intosc_hs_div2_clk (60 to 200 MHz)