Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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10.3.15.4.2. Configuring AxUSER[4:0] Sideband Signals

The following list highlights how to correctly derive and apply the correct AxUSER settings for coherent accesses.
  • AxUSER[0] (shared attribute) must be set to 0x1 for coherent accesses.
  • Because the ACP has no inner cache policy, AxUSER[3:1] is not interpreted by the SCU. AxUSER[3:1] attributes pass to the L2 cache controller and are used when the cache is operating in exclusive mode.
  • For FPGA masters, AxUSER[4:0] is applied in the FPGA fabric and can be set for each access.