Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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16.4.14. Interrupts

All interrupt sources are combined to create a single level-sensitive, active-high interrupt (qspi_intr). Software can determine the source of the interrupt by reading the interrupt status register (irqstat). By default, the interrupt source is cleared when software writes a one (1) to the interrupt status register. The interrupts are individually maskable through the interrupt mask register (irqmask). The Interrupt Sources in the irqstat Register table lists the interrupt sources in the irqstat register.

Table 175.  Interrupt Sources in the irqstat Register

Interrupt Source

Description

Underflow detected

When 0, no underflow has been detected. When 1, the data slave write data is being supplied too slowly. This situation can occur when data slave write data is being supplied too slowly to keep up with the requested write operation This bit is reset only by a system reset and cleared only when a 1 is written to it.

Indirect operation complete

The controller has completed a triggered indirect operation.

Indirect read reject

An indirect operation was requested but could not be accepted because two indirect operations are already in the queue.

Protected area write attempt

A write to a protected area was attempted and rejected.

Illegal data slave access detected

An illegal data slave access has been detected. Data slave wrapping bursts and the use of split and retry accesses can cause this interrupt. It is usually an indicator that soft masters in the FPGA fabric are attempting to access the HPS in an unsupported way.

Transfer watermark reached

The indirect transfer watermark level has been reached.

Receive overflow

This condition occurs only in legacy SPI mode. When 0, no overflow has been detected. When 1, an over flow to the RX FIFO buffer has occurred. This bit is reset only by a system reset and cleared to zero only when this register is written to. If a new write to the RX FIFO buffer occurs at the same time as a register is read, this flag remains set to 1.

TX FIFO not full

This condition occurs only in legacy SPI mode. When 0, the TX FIFO buffer is full. When 1, the TX FIFO buffer is not full.

TX FIFO full

This condition occurs only in legacy SPI mode. When 0, the TX FIFO buffer is not full. When 1, the TX FIFO buffer is full.

RX FIFO not empty

This condition occurs only in legacy SPI mode. When 0, the RX FIFO buffer is empty. When 1, the RX FIFO buffer is not empty.

RX FIFO full

This condition occurs only in legacy SPI mode. When 0, the RX FIFO buffer is not full. When 1, the RX FIFO buffer is full.

Indirect read partition overflow

Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation