Intel® Arria® 10 Hard Processor System Technical Reference Manual
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10.3.15.7. Avoiding ACP Dependency Lockup
- The CPU initiates a device memory access to the FPGA fabric. The CPU pipeline must stall until this type of access is complete.
- Before the FPGA fabric state machine can respond to the device memory access, it must access the HPS coherently. It initiates a coherent access, which requires the ACP.
- The ACP must perform a cache maintenance operation before it can complete the access. However, the CPU’s pipeline stall prevents it from performing the cache maintenance operation. The system deadlocks.
You can implement the desired access without deadlock, by breaking it into smaller pieces. For example, you can initiate the operation with one access, then determine the operation status with a second access.