Intel® Arria® 10 Hard Processor System Technical Reference Manual
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30.1. Simulation Flows
Intel provides a functional register transfer level (RTL) simulation and a post–fitter gate–level simulation flow. Both simulation flows involve the following major steps, which is defined in the following sections:
- Setting up the HPS component for simulation.
- Generating the HPS simulation model in Platform Designer (Standard).
- Running the simulation.