Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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21.5.4. Abort Transfer

The ABORT control bit of the IC_ENABLE register allows the software to relinquish the I2C bus before completing the issued transfer commands from the Tx FIFO. In response to an ABORT request, the controller issues the STOP condition over the I2C bus, followed by Tx FIFO flush. Aborting the transfer is allowed only in master mode of operation.†

  1. Stop filling the Tx FIFO (IC_DATA_CMD) with new commands.†
  2. When operating in DMA mode, disable the transmit DMA by setting TDMAE to 0. †
  3. Set bit 1 of the IC_ENABLE register (ABORT) to 1.†
  4. Wait for the M_TX_ABRT interrupt.†
  5. Read the IC_TX_ABRT_SOURCE register to identify the source as ABRT_USER_ABRT.†