Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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6.3.4. FPGA Interface Enables

The system manager can enable or disable interfaces between the FPGA and HPS.

The global interface bit (intf) of the global disable register (gbl) disables all interfaces between the FPGA and HPS.

Note: Ensure that the FPGA in configured before enabling the interfaces and that all interfaces between the FPGA and HPS are inactive before disabling them.

You can program the individual disable register (indiv) to disable the following interfaces between the FPGA and HPS:

You can program the FPGA interface enable registers (fpgaintf_en_*) to disable the following interfaces between the FPGA and HPS:

  • Reset request interface
  • JTAG enable interface
  • I/O configuration interface
  • Boundary scan interface
  • Debug interface
  • Trace interface
  • System Trace Macrocell (STM) interface
  • Cross-trigger interface (CTI)
  • QSPI interface
  • SD/MMC interface
  • SPI Master interface
  • SPI Slave interface
  • EMAC interface
  • UART interface