Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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17.3.1.1. Peripheral Request Interface Mapping

You can assign a peripheral request interface to any of the DMA channels. When a DMA channel thread executes DMAWFP, the value programmed in the peripheral [4:0] field specifies the peripheral associated with that DMA channel.

The DMAC supports 32 peripheral request handshakes. Each request handshake can receive up to four outstanding requests, and is assigned a specific peripheral device ID. The following table lists the peripheral device ID assignments.

Table 176.  Peripheral Request Interface Mapping

Peripheral

Request Interface ID

Protocol

FPGA 0

0

Synopsys*

FPGA 1

1

Synopsys*

FPGA 2

2

Synopsys*

FPGA 3

3

Synopsys*

FPGA 4

4

Synopsys*

FPGA 5/Security Manager DMA Tx

5

Synopsys*

FPGA 6/I2C EMAC2 Tx

6

Synopsys*

FPGA 7/I2C EMAC2 Rx

7

Synopsys*

I2C0 Tx

8

Synopsys*

I2C0 Rx

9

Synopsys*

I2C1 Tx

10

Synopsys*

I2C1 Rx

11

Synopsys*

I2C EMAC0 Tx

12

Synopsys*

I2C EMAC0 Rx

13

Synopsys*

I2C EMAC1 Tx

14

Synopsys*

I2C EMAC1 Rx

15

Synopsys*

SPI0 Master Tx

16

Synopsys*

SPI0 Master Rx

17

Synopsys*

SPI0 Slave Tx

18

Synopsys*

SPI0 Slave Rx

19

Synopsys*

SPI1 Master Tx

20

Synopsys*

SPI1 Master Rx

21

Synopsys*

SPI1 Slave Tx

22

Synopsys*

SPI1 Slave Rx

23

Synopsys*

Quad SPI Flash Tx

24

Arm*

Quad SPI Flash Rx

25

Arm*

STM

26

Arm*

FPGA Manager DMA Rx

27

Synopsys*

UART0 Tx

28

Synopsys*

UART0 Rx

29

Synopsys*

UART1 Tx

30

Synopsys*

UART1 Rx

31

Synopsys*