Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

14.2. NAND Flash Controller Block Diagram and System Integration

Figure 59. NAND Flash Controller Block DiagramThe following figure shows integration of the NAND flash controller in the HPS.

Features of the flash controller:

  • Receives commands and data from the host through memory-mapped control and data registers connected to the command and data slave interface
  • The host accesses the flash controller’s control and status registers (CSRs) through the register slave interface.
  • Handles all command sequencing and flash device interactions
  • Generates interrupts to the HPS Cortex*-A9 MPCore*
  • The DMA master interface provides accesses to and from the flash controller through the controller's built‑in DMA.